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16-bit adder, and implementation method thereof, operational circuit and chip

An adder and addend technology, applied in the circuit field, can solve the problems of long time consumption and low calculation speed, and achieve the effect of increasing calculation speed and shortening time

Pending Publication Date: 2021-09-17
北京源启先进微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

By analogy, when calculating the summation result of the 15th bit, first obtain the carry output of the 14th bit in the carry chain, the entire calculation process takes a long time and the calculation speed is low

Method used

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  • 16-bit adder, and implementation method thereof, operational circuit and chip
  • 16-bit adder, and implementation method thereof, operational circuit and chip
  • 16-bit adder, and implementation method thereof, operational circuit and chip

Examples

Experimental program
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Effect test

Embodiment 1

[0027] figure 1 It is a schematic structural diagram of an adder provided in the embodiment of the present application. The adder in this embodiment may be an independent hardware circuit structure, or may be a basic circuit unit structure of other devices such as a chip or a microprocessor. Such as figure 1 As shown, the 16-bit adder provided by the embodiment of the present application includes N carry modules 10 , where N is an integer greater than 1 and less than 15. Each carry module corresponds to a plurality of bits in the first addend and the second addend, wherein the first addend and the second addend are 16-bit binary numbers. For example, one carry module may correspond to 2 bits, 3 bits or more bits in the first addend and the second addend. It should be understood that the number of bits in the first addend and the second addend corresponding to each of the N carry modules 10 may be the same or different.

[0028] Wherein, the nth carry module is connected wi...

Embodiment 2

[0054] Based on the 16-bit adder provided in Embodiment 1, further, this embodiment provides figure 1 Schematic diagram of the structure of a carry module in the 16-bit adder shown. It should be understood that the carry module may be any one of the N carry modules in Embodiment 1. For the convenience of description, this carry module is referred to as the nth carry module hereinafter. In this embodiment, the pre-processing unit included in the nth carry module includes at least one first pre-processing unit and at least one second pre-processing unit arranged alternately.

[0055] In this embodiment, the first preprocessing unit is used to perform operations on the i-th bit and the i-1th bit in the corresponding first and second addends to generate the first preprocessing result, and the first A preprocessing result indicates a logical OR operation result of the carry generating signal of the i-th bit and the i-1th bit, where i is an odd number.

[0056] Optionally, in a sp...

Embodiment 3

[0082] Based on the 16-bit adder provided in the foregoing embodiments, this embodiment of the present application provides a method for implementing a 16-bit adder. Figure 6 It is a flow chart of an implementation method of a 16-bit adder provided by the embodiment of the present application. Such as Figure 6 As shown, the implementation of the 16-bit adder includes:

[0083] S601. Receive the first addend and the second addend, the first addend and the second addend are divided into N data groups according to the order of the bits from low to high, and each data group includes the first addend and the second Multiple bits in the addend, N is an integer greater than 1 and less than 15;

[0084] S602. Perform preprocessing on multiple bits included in each data group;

[0085] S603. Calculate the carry output of multiple bits contained in each data group, wherein, for the nth data group in the N data groups, according to the preprocessing result of the nth data group and ...

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Abstract

The embodiment of the invention provides a 16-bit summator, and an implementation method thereof, an operational circuit and a chip. The 16-bit summator comprises N carry modules and a summation module, each carry module corresponds to a plurality of bits in the first addend and the second addend, and comprises a preprocessing unit and a plurality of carry calculation units; a preprocessing unit included in the nth carry module is used for preprocessing a plurality of bits in the corresponding first addend and second addend; a plurality of carry calculation units included in the nth carry module are used for carrying out operation according to the preprocessing result and the inter-stage carry parameter of the (n-1) th carry module to generate carry output of each bit corresponding to the nth carry module and the inter-stage carry parameter of the nth carry module, and parallel calculation of carry output of each bit in the 16-bit binary data is basically realized for summation operation, so that the duration of the whole calculation process can be shortened, and the calculation speed is improved.

Description

technical field [0001] The embodiments of the present application relate to the field of circuits, and in particular to a 16-bit adder and its implementation method, an arithmetic circuit and a chip. Background technique [0002] A 16-bit adder is one of the commonly used circuits in digital circuit design. For example, a 16-bit adder is often used in complex logic chips such as a central processing unit (CPU) and a graphics processing unit (GPU). It is often used in comprehensive design chips such as Microcontroller Unit (MCU), Field Programmable Gate Array (Field Programmable Gate Array, FPGA). [0003] In the related art, when the 16-bit adder calculates the summation result of each bit, it usually needs to obtain the carry output of the adjacent previous bit first. For example, when calculating the summation result of the second bit, it needs to first obtain For the carry output of the first bit, when calculating the summation result of the third bit, it is necessary to...

Claims

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Application Information

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IPC IPC(8): G06F7/50
CPCG06F7/50
Inventor 不公告发明人
Owner 北京源启先进微电子有限公司
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