High-voltage-resistant p-channel LDMOS device and preparation method thereof
A high withstand voltage and channel technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as harsh process conditions and limiting LDMOS AC characteristics, and achieve small parasitic capacitance, good high-frequency characteristics, The effect of small additional capacitance
Pending Publication Date: 2021-09-17
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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Problems solved by technology
However, in the super junction process, the doping concentration and thickness of the P region and the N region are strictly controlled, which makes the process conditions harsh.
On the other hand, the PN junction area of the super junction structure is limited by the contact area between the P region and the N region, so the parasitic capacitance increased by the introduction of the super junction structure greatly limits the AC characteristics of LDMOS
Method used
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[0035] The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.
[0036] Such as figure 2 As shown, a high withstand voltage p-channel LDMOS device provided by Embodiment 1 of the present invention includes a semiconductor substrate 1, a p-type lightly doped drift region 2, an n-type well region 3, a gate structure, a p-type heavy doped source 6 and p-type heavily doped drain 7;
[0037] The n-type well region 3 is located on one side of the top layer of the semiconductor substrate 1, the p-type lightly doped drift region 2 is located on the other side of the top layer of the semiconductor substrate 1; the p-type heavily doped drain 7 is located on the p-type lightly doped The top layer of the doped drift region 2 is away from the side of the n-type well region 3, and the p-type...
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The invention relates to a high-voltage-resistant p-channel LDMOS device, and belongs to the technical field of semiconductors. A surface super-junction structure is provided for the p-channel LDMOS device, comb-finger-shaped n-type semiconductor strips are prepared on the surface of a drift region of the device, the n-type semiconductor strips are electrically connected with a source electrode, large-range depletion of a drift region channel can be achieved under the turn-off condition, the depletion region can tolerate a higher voltage, so the breakdown characteristic of the device is enhanced. On the other hand, compared with a traditional super junction, the comb-finger-shaped n-type surface voltage-withstanding structure is prepared on the surface of the drift region and does not need to be embedded into the drift region of the device, and the requirement for the technology is lowered. Meanwhile, since the comb-finger-shaped n-type surface voltage-withstanding structure connected with the source electrode only covers a small part of the drift region area, when the device is switched on, parasitic resistance and parasitic capacitance associated with the device are smaller, so the device has better direct-current conduction characteristic and high-frequency characteristic.
Description
technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a high withstand voltage p-channel LDMOS device and a preparation method thereof. Background technique [0002] In the field of radio frequency and power integrated circuits, the characteristics of frequency, withstand voltage, and on-resistance of devices are important performance indicators that determine circuit characteristics. At present, with the continuous improvement of the integration level of power integrated circuits, the requirements for various characteristics of circuits and devices are also getting higher and higher. Among RF power devices, LDMOS (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) devices, compared with other power devices, exhibit high reliability, high linearity and other excellent electrical characteristics, as well as the advantages of being compatible with traditional CMOS processes. As a research hotspot...
Claims
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Login to View More IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/7816H01L29/0634H01L29/66681
Inventor 罗谦文厚东姜玄青范镇
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA