Error rate analysis method, system and device for MLC chip

Abstract

The invention discloses an error rate analysis method, system and device for an MLC chip. The method comprises the steps of selecting a data block from the MLC chip, and carrying out the erasing operation of the data block; after the erasing operation is completed, reading each group of double bits corresponding to each first page and each second page of the data block, and determining the bit state of each group of double bits; counting a first total number of all double bits corresponding to the target page in a target bit state representing a data writing error so as to obtain a first error rate of the target page in the target bit state; and counting a second total number of all the double bits corresponding to the data block in the target bit state to obtain a second error rate of the data block in the target bit state, and analyzing the chip performance based on the first / second error rate. Therefore, the error rate analysis can be carried out on the specific data blocks and pages of the MLC chip, the error rates of the specific data blocks and pages can be analyzed in different bit states, and comprehensive performance analysis of the MLC chip is facilitated.

Description

Technical field [0001] The present invention relates to a storage, and more particularly relates to an error rate is one kind of MLC chips analytical method, system and apparatus. Background technique [0002] Currently, NAND Flash (non-volatile flash memory) is widely used for a variety of storage applications, its architecture, it is divided into SLC (Single-Level Cell, single memory cell, referring to the storage unit may be a storing data of one bit, 0 and 1 in both cases), MLC (Multi-Level cell, double the memory cell, referring to a storage unit can store data of 2 bits, there are (11,10,01 , 00) four cases) and TLC (Triple-Level cell, three memory cell, referring to a storage unit can store data of 3 bits, there are (000,001,010,011,100,101,110 , 111) eight situations) three. Wherein, the current mainstream MLC chips are memory chips, chip performance MLC MLC chips depends on the error rate of written data (will be appreciated that the higher the error rate of written data...

AI Technical Summary

Problems solved by technology

However, the single-bit global analysis method cannot analyze the error rate of the specific data block (block) and page (page) of the MLC chip, which is not conducive to a comprehensive analysis of the performance of the MLC chip

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