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Multi-bump packaging structure and manufacturing method thereof

A packaging structure and bump technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve problems such as performance degradation and failure, achieve improved performance, a large stress tolerance range, and is conducive to The effect of miniaturization

Active Publication Date: 2021-11-26
FOREHOPE ELECTRONICS NINGBO CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention includes, for example, to provide a multi-bump packaging structure and its preparation method, which can solve the problem of performance degradation and failure caused by stress acting on the chip soldering point in the prior art

Method used

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  • Multi-bump packaging structure and manufacturing method thereof
  • Multi-bump packaging structure and manufacturing method thereof
  • Multi-bump packaging structure and manufacturing method thereof

Examples

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no. 1 example

[0052] see figure 1 , this embodiment provides a multi-bump packaging structure 100, which can solve the problem of product performance degradation or even failure caused by the stress caused by the mismatch of thermal expansion coefficients acting on the chip bump (soldering point) in the conventional technology, and improve The reliability of the package structure is improved, the problem of cracks is avoided, and it is beneficial to the miniaturization of the product and improves the performance of the product. It also avoids the hidden cracks of the UBM layer and the internal circuit layer caused by TBD soldering, and further ensures the reliability of the package structure.

[0053] The multi-bump packaging structure 100 provided in this embodiment includes a wafer substrate 110, a protective layer 120, a first wiring layer 130, a first conductive bump 140, a first dielectric layer 150, a second wiring layer 160 and a second wiring layer 160. Conductive bumps 170, wherei...

no. 2 example

[0069] see figure 2 , this embodiment provides a multi-bump packaging structure 100, its basic structure and principle and the technical effects produced are the same as those of the first embodiment, for a brief description, for the part not mentioned in this embodiment, please refer to the first Corresponding content in the embodiment.

[0070] In this embodiment, the multi-bump packaging structure 100 includes a wafer substrate 110, a protective layer 120, a first wiring layer 130, a first conductive bump 140, a first dielectric layer 150, a second wiring layer 160 and a second Conductive bumps 170, wherein one side surface of the wafer substrate 110 is provided with a metal pad 111, the protection layer 120 is provided on the side of the wafer substrate 110 with the metal pad 111, and the protection layer 120 is provided with a pad opening 113 The pad opening 113 corresponds to the metal pad 111 and penetrates to the surface of the metal pad 111 , so that the metal pad 1...

no. 3 example

[0075] see image 3 , this embodiment provides a multi-bump packaging structure 100, its basic structure and principle and the technical effects produced are the same as those of the first embodiment, for a brief description, for the part not mentioned in this embodiment, please refer to the first Corresponding content in the embodiment.

[0076] The multi-bump packaging structure 100 provided in this embodiment includes a wafer substrate 110, a protective layer 120, a first wiring layer 130, a first conductive bump 140, a first dielectric layer 150, a second wiring layer 160 and a second conductive Protrusion 170, wherein one side surface of the wafer base 110 is provided with a metal pad 111, the protection layer 120 is provided on the side of the wafer base 110 with the metal pad 111, and the protection layer 120 is provided with a pad opening 113, The pad opening 113 corresponds to the metal pad 111 and penetrates to the surface of the metal pad 111 , so that the metal pa...

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Abstract

Embodiments of the present invention provide a multi-bump packaging structure and a preparation method thereof, which relate to the technical field of semiconductor packaging. The multi-bump packaging structure includes a wafer substrate, a protective layer, a first circuit layer, and a first conductive bump. , the first dielectric layer, the second circuit layer and the second conductive bump, because different circuit layers are used to realize the connection between the first conductive bump and the second conductive bump, the stress tolerance range is larger, so that the first When the conductive bump and the second conductive bump are stressed, the UBM layer at the bottom is not easy to fall off, which greatly improves the reliability of the metal bump in the traditional packaging structure and avoids the problem of hidden cracks. At the same time, the present invention adopts the arrangement of multiple circuit layers, which can make the first conductive bump and the second conductive bump relatively close together, thereby making the metal bumps denser, which is beneficial to the miniaturization of the product and improves the product quality. performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a multi-bump packaging structure and a preparation method thereof. Background technique [0002] With the rapid development of the semiconductor industry, the flip-chip packaging structure is widely used in the semiconductor industry. The flip-chip packaging utilizes bumps to electrically connect the chip and the substrate. The bump includes a copper pillar, a metal layer (UBM: under bumpmetalization) and a passivation layer. The material is mostly FR4 resin or BT resin. Under the influence of external mechanics, time, temperature, humidity and other conditions, the substrate will undergo irreversible plastic deformation. At the same time, the chip material silicon (thermal expansion coefficient of 2.5 ppm / C ) and the substrate material (the thermal expansion coefficient is 12 ppm / C) will act on the chip bump (soldering point) due to the stress caused by the mism...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L21/60
CPCH01L24/14H01L24/11H01L2224/141H01L2224/14104H01L2224/11
Inventor 何正鸿徐玉鹏钟磊李利
Owner FOREHOPE ELECTRONICS NINGBO CO LTD
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