Microprocessor and prefetched instruction adjusting method

Abstract

The invention relates to a microprocessor and a prefetched instruction adjusting method. In one embodiment, the microprocessor includes a first logic configured to dynamically adjust a maximum prefetched instruction count based on a total count of branches predicted to be taken on a predetermined number of cache lines; and a second logic configured to pre-fetch the instruction based on the adjusted maximum pre-fetch count.

Description

technical field [0001] The present invention relates generally to microprocessors, and more particularly to prefetching in microprocessors. Background technique [0002] As the microprocessor executes program instructions, the microprocessor uses the processor bus to fetch instructions from memory into the microprocessor. The time required to fetch an instruction from memory may consume many clock cycles (eg, hundreds of clock cycles). To alleviate this problem, microprocessors include cache memory. Cache memory (usually much smaller than system memory) is memory inside a microprocessor (or processor core) that is used to store a subset of instructions located in system memory. Although prefetching is important for both instructions and data, the emphasis here is on the instruction cache. When a microprocessor fetches an instruction, the microprocessor checks to see if the instruction is present in the cache and valid. If so, instructions can be executed faster than if t...

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Problems solved by technology

On the other hand, if too much information is prefetched (for example, too many cache lines), the prefetcher may be less efficient and other system resources and bandwidth may be overburdened

Also, if the cache is full, new cache lines are prefetched into the cache, which may cause other cache lines to be evicted from the cache

Thus, cache lines that were in cache due to previous need may be evicted by lines that may only be needed in the future

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