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Centralized DFE reset generator for a memory device

一种发生器、存储器的技术，应用在静态存储器、数字存储器信息、信息存储等方向，能够解决消耗裸片空间功率等问题

Active Publication Date: 2021-10-19
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, including a DFE reset generator in each DQ may consume die space and / or power for the memory device

Method used

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  • Centralized DFE reset generator for a memory device
  • Centralized DFE reset generator for a memory device
  • Centralized DFE reset generator for a memory device

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0015] One or more specific embodiments are described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design initiative, a number of implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related Constraints, the target may vary from implementation to implementation. Furthermore, it should be appreciated that such a development effort might be complex and time consuming, but would nonetheless be a routine undertaking of design, production, and manufacture for those of ordinary skill having the benefit of this disclosure.

[0016] A decision feedback equalizer (DFE) can utilize a DFE buffer to track previous data levels to account for incoming data levels. Between write operati...

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PUM

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Abstract

The invention relates to a centralized DFE reset generator for a memory device. Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

Description

technical field [0001] Embodiments of the present disclosure relate generally to the field of decision feedback equalizers (DFEs) for memory devices. More specifically, embodiments of the present disclosure relate to resetting taps of a DFE using a centralized DFE reset generator. Background technique [0002] Semiconductor devices (eg, memory devices) utilize timing and phase shifting of data signals, data strobes, and / or other signals to perform operations (eg, write operations). The DFE can be used to maintain a buffer of multiple (eg, 4) previous data bits to improve the accuracy of interpreting whether the current bit is high or low. For example, if the DFE has stored 4 previous low data bits, the data line (DQ) will be at a lower voltage level and the current data bit should be interpreted as logic high or low relative to said level . These multi-tap DFE input buffers are used to allow resolution of smaller external data eyes. However, including a DFE reset generat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4076
CPCG11C11/4076G11C11/4093H04L25/03146H04L25/03878H04L25/0278G11C7/1087G11C7/1093H04L25/03267G11C11/4096
Inventor W·C·沃尔德罗普D·B·彭妮
Owner MICRON TECH INC