Chip verification system and method
A verification system and chip technology, applied in functional inspection, instrumentation, error detection/correction, etc., can solve the problems of increasing the complexity of chip verification work and reducing the efficiency of chip verification, so as to improve the efficiency of chip verification and reduce the complexity. Effect
Pending Publication Date: 2021-10-22
BEIJING ESWIN COMPUTING TECH CO LTD
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In this way, the complexity of the chip verification work operation will be increased, and the efficiency of chip verification will be reduced.
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[0020] Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided for thorough understanding of the application and to fully convey the scope of the application to those skilled in the art.
[0021] It should be noted that, unless otherwise specified, technical terms or scientific terms used in this application shall have the usual meanings understood by those skilled in the art to which this application belongs.
[0022] In the existing chip verification system, based on the same functional module and the same functional specification, when different chips are tested, the implementation details will be different, and there may be trade...
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The invention provides a chip verification system and method, and the system comprises a test event module which is used for transmitting a test instruction, wherein the test instruction is an instruction generated based on a script, and the test instruction is used for verifying the function of a to-be-tested chip; a signal generation module which is used for generating a hardware signal adaptive to the to-be-tested chip according to the test instruction; a to-be-tested module which is used for placing a to-be-tested chip, so that the to-be-tested chip receives the hardware signal and responds to the hardware signal to generate output data; and a comparison module which is used for acquiring the output data and determining whether the to-be-tested chip passes verification according to a comparison result of the output data and preset data, wherein the preset data is data output by the to-be-tested chip in response to the hardware signal under the condition that the function is normal. No matter how the hardware information of the to-be-tested chip changes, the signal generation module can generate the hardware signal adaptive to the to-be-tested chip based on the test instruction, so that the corresponding function of the to-be-tested chip is verified, and the chip verification efficiency is improved.
Description
technical field [0001] The present application relates to the field of chip technology, in particular to a chip verification system and method. Background technique [0002] The so-called chip verification refers to the use of corresponding verification languages, verification tools, and verification methods to verify whether the design of the chip meets the expected functions of the chip before chip production, and to find corresponding defects. [0003] At present, for chip verification, front-end verification is mainly based on Universal Verification Methodology (UVM). Specifically, code verification and verification technology (Verification IP, VIP) is used to generate an incentive drive, so that the internal signal of the chip in the module to be verified is reversed, and then related function points are triggered to generate output. Then, compare the output with the output of the comparison module, and then determine whether the chip has passed the verification accord...
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IPC IPC(8): G06F11/22G06F11/26G06F30/398
CPCG06F11/2236G06F11/2247G06F11/26G06F30/398
Inventor 郭向飞陈玉平
Owner BEIJING ESWIN COMPUTING TECH CO LTD