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Forming method of semiconductor structure

A semiconductor and pseudo-gate structure technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problem that the electrical performance of GAA structure MOSFET needs to be improved, and achieve the effect of improving the performance of semiconductor structure and performance.

Active Publication Date: 2021-10-26
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the electrical performance of the GAA structure MOSFET in the prior art still needs to be improved

Method used

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  • Forming method of semiconductor structure
  • Forming method of semiconductor structure
  • Forming method of semiconductor structure

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Embodiment Construction

[0031] As mentioned in the background art, the electrical performance of the GAA structure MOSFET in the prior art still needs to be improved. The following will describe in detail with reference to the accompanying drawings.

[0032] Please refer to figure 1 , providing a substrate 100; forming a fin structure on the substrate 100, the fin structure includes several layers of sacrificial layers 101 overlapping along the normal direction of the substrate surface, and the sacrificial layer 101 located in two adjacent layers A channel layer 102 between the layers 101; a dummy gate structure 103 across the fin structure is formed on the substrate 100, and the dummy gate structure 103 covers part of the sidewall and part of the fin structure top surface.

[0033] Please refer to figure 2 Forming source and drain grooves 104 in the fin structures on both sides of the dummy gate structure 103 ; removing part of the sacrificial layer 101 exposed from side walls of the source and...

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Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a fin structure on a substrate, the fin structure comprising a plurality of channel layers and a sacrificial layer, first semiconductor atoms being arranged in the sacrificial layer, and the atomic percent concentration of the first semiconductor atoms in the sacrificial layer being gradually reduced layer by layer from the bottom to the top of the fin structure. The atomic percent concentration of the first semiconductor atoms in the sacrificial layer is gradually reduced layer by layer from the bottom to the top of the fin structure, and the etching rate is in direct proportion to the atomic percent concentration of the first semiconductor atoms in the sacrificial layer, so that the etching rate of the sacrificial layer at the bottom layer is higher; therefore, the depths of the finally formed fin part grooves tend to be consistent, and the performance of the finally formed MOS structures tends to be consistent, so that the performance of the final semiconductor structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] Metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most important elements in the modern integrated circuit, and the basic structure of MOSFET comprises: semiconductor substrate; Be positioned at the gate structure of semiconductor substrate surface, described gate structure comprises : a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; source and drain doped regions in the semiconductor substrate on both sides of the gate structure. [0003] With the further development of semiconductor technology, conventional fin field effect transistors have limitations in further increasing the operating current. Specifically, since only the area close to the top surface and the side...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66803H01L29/785H01L29/66545
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP