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Bit-ordered binary-weighted multiplier-accumulator

A matrix multiplier, binary coding technology, applied in the direction of instruments, complex mathematical operations, calculations, etc., can solve problems such as large processing resources and/or energy, consumption, etc.

Pending Publication Date: 2021-12-17
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] Executing this equation (when performed digitally) can consume significant processing resources and / or energy
Traditional analog component parts or mixed digital and analog component parts may require a relatively large number of clock cycles, and / or a relatively large real estate area to implement

Method used

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  • Bit-ordered binary-weighted multiplier-accumulator
  • Bit-ordered binary-weighted multiplier-accumulator
  • Bit-ordered binary-weighted multiplier-accumulator

Examples

Experimental program
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Embodiment approach 300

[0031] Embodiment 300 includes: capacitor-switch array 302 . Capacitors may be order-weighted, which means that the capacitance of each capacitor may be selected to passively store an amount of charge weighted for a particular order. As an example, in order to output a value of 4 bits, there are 4 capacitors. Capacitor 316-1 may be used to store charge corresponding to the LSB. Thus, capacitor 316-1 may have a capacitance of C (where C is a unity value). Capacitor 316-2 may be used to store charge corresponding to the second LSB. Thus, capacitor 316-2 may have a capacitance of 2C (which represents a weight of 2 times C, corresponding to the second LSB in the bit order in binary). Capacitor 316-3 may be used to store charge corresponding to the second MSB. Thus, capacitor 316-3 may have a capacitance of 4C. Capacitor 316-4 may be used to store charge corresponding to the MSB. Thus, capacitor 316-4 may have a capacitance of 8C. Each capacitor has a capacitance correspondi...

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Abstract

Various arrangements for performing vector-matrix multiplication are provided here. Digital input vectors that include binary-encoded values can be converted into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs). Using an analog vector matrix multiplier, a vector-matrix multiplication operation can be performed using a weighting matrix for each bit-order of the plurality of analog signals. For each performed vector-matrix multiplication operation, a bit-ordered indication of an output of the analog vector matrix multiplier may be stored. A bit-order weighted summation of the sequentially performed vector-matrix multiplication operation may be performed.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of priority to US Patent Application No. 16 / 408,509, filed May 9, 2019, the entire disclosure of which is incorporated herein by reference for all purposes. Background technique [0003] Vector-matrix multiplication can be defined as the sum of the products of vectors and matrices. Specifically, Equation 1 may be used to define a vector matrix multiplication operation in which the products are summed. [0004] Y=∑ i W ij x i Equation 1 [0005] In Equation 1, Xi is an input vector consisting of numerical values ​​(which can be represented using binary bits in an electronic environment), and Wij represents matrix weighted values. Y is the output vector obtained by summing the product vectors. This function has applications in various signal processing, image processing, and artificial intelligence applications (for example, in the use of neural networks). [0006] Performing thi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/16G06F7/491G06F7/498
CPCG06F17/16G06F7/5443G06F2207/4828H03M1/804G06F7/4915G06F7/4985H03M1/74
Inventor 颜世骅弗兰克·曾文·郭
Owner APPLIED MATERIALS INC