Data exchange method and device based on FPGA memory dynamic allocation

Abstract

The invention relates to a data exchange method and device based on FPGA (Field Programmable Gate Array) memory dynamic allocation, which adopts a field programmable FPGA device to realize Ethernet two-layer exchange processing service, and a memory dynamic allocation strategy is used, that is, an RAM (Random Access Memory) in the FPGA is used to realize that a first-level cache unit and a second-level cache unit are used as forwarding message cache; and the first-level cache unit caches the Ethernet message subjected to two-layer exchange processing, and the second-level cache unit dynamically allocates the Ethernet message to a certain port in which the message is suddenly transmitted. Generally, only the first-level cache unit is used as a forwarding message cache, when the instantaneous flow of a certain port is too large, the second-level cache unit is applied to be occupied, the second-level cache unit is released after the message is sent, the second-level cache unit is dynamically allocated to the port with the large instantaneous flow, the FPGA internal cache is reasonably and efficiently used, and the FPGA internal cache utilization rate is improved. And an SDRAM (Synchronous Dynamic Random Access Memory) required to be mounted by a conventional message caching strategy is omitted.

Description

technical field [0001] The invention relates to the technical field of communication and power system automation, in particular to a data exchange method and device based on FPGA memory dynamic allocation. Background technique [0002] With the continuous development of digitalization and intelligence in substations, there are more and more requirements for the diversification and individualization of network communication, and the limitations of traditional network switching chips are becoming more and more obvious. It is suitable for busbar protection devices of various voltage levels up to 1000kV, including main box and sub-box. The main box must complete SV sampling and GOOSE tripping functions through the network. Receive and communicate with the host, the network topology of the bus protection device is as follows figure 1 As shown, the sub-machine communicates with the external cascade of the host through switch port 5, and the sub-machine switch port 1 to port 4 com...

AI Technical Summary

Problems solved by technology

When the network topology changes, the network switching chip cannot change its own structure, and its use will be limited; currently, the network switching implemented by FPGA will use an external SRAM memory for temporary storage and forwarding of network packets, and the hardware cost and implementation complexity are high.

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