A network-on-chip router

Abstract

The invention relates to an on-chip network router. The input buffer unit in the router temporarily stores the first-in-first-out cache queues in different directions; the routing calculation-link allocation unit determines the data selection signal, read enable signal and write enable signal according to the data input signal and queue capacity signal; The switch unit controls the data input signal transmission from the input buffer unit to the output buffer unit according to the data selection signal; the flow control unit controls the data transmission rate and determines the read usage between the adjacent routers according to the data input signal of the input buffer unit and the queue capacity signal. The output buffer unit is controlled by the enable signal; the output buffer unit controls the destination of the data input signal according to the write enable signal of the output buffer unit determined by the routing calculation-link allocation unit and the read enable signal determined by the flow control unit. The invention can avoid congestion of the on-chip network, improve the global traffic distribution of the on-chip network, and increase the utilization rate and throughput rate of the on-chip network.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to an on-chip network router. Background technique [0002] Traditional single-core processors rely on the reduction of transistor feature size and continuously increase the clock frequency to improve performance, but when the transistor size is reduced to a certain extent, it becomes very difficult to improve the performance of single-core processors. The bottleneck of single-core processor performance improvement has prompted the emergence of multi-core systems. By splitting a complex single-core processor into multiple parallel simple cores, multi-threaded tasks can be executed in parallel, which greatly improves the performance of the system. throughput rate. [0003] At the same time, the bottleneck of the processor system has changed from improving the performance of a single-core system processor to improving the communication performance between multiple cores. With th...

AI Technical Summary

Problems solved by technology

However, for high traffic loads, the NOC may have serious congestion problems, which prevents the NOC from achieving the desired performance.

[0005] For medium and low network traffic loads, the data reception rate of the network on chip is the same as the data injection rate, but if the injected data flow reaches (or exceeds) a certain threshold, the data flow that the network on chip can receive will decrease, and the network on chip The data transmission delay in the network will also be greatly increased, which greatly reduces the transmission performance of the network on chip

The performance degradation occurs because, in the case of high network traffic, several packets compete for the same resource (the data cache channel of the adjacent router), but since only one packet can use them, the remaining packets are lost in the network Stalls in the middle, waiting for the allocation of available resources, thereby blocking the transmission of other packets

[0006] That is, the optimization strategy of traditional network-on-chip routers for network traffic focuses on the optimization of routing calculation algorithms. However, in order to avoid deadlocks, livelocks, etc., the optimization of routing algorithms is greatly restricted, and the network-on-chip has many traffic patterns. Algorithm optimization is difficult to cover all traffic patterns, and the versatility is poor

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