Semiconductor module substrate and design method
A semiconductor and substrate technology, which is applied in the field of semiconductor module substrate and design, can solve the difficulty of suppressing the stray inductance of the common source of the gate-level drive circuit of the chip, increase the misconduction of the transient bridge arm of the commutation, and the serious problem of chip serial heat and other problems, to achieve the effect of convenient and accurate location of fault generation mechanism, reduction of coupling inductance and its relative error, high thermal reliability and electrical reliability
Pending Publication Date: 2021-12-31
LEADRIVE TECH (SHANGHAI) CO LTD
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Problems solved by technology
However, the increase in the number of parallel connections makes the steady-state and dynamic current sharing analysis of each chip branch more complicated, and the problem of series heat between chips is more serious, resulting in inconsistent junction temperatures of each chip and lower thermal reliability.
At the same time, it is more difficult to suppress the stray inductance of the common source of the gate-level drive circuit of each chip, which increases the risk of false conduction of the bridge arm during the commutation transient and reduces the electrical reliability.
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[0061] The advantages of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.
[0062] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present disclosure as recited in the appended claims.
[0063] The terminology used in the present disclosure is for the purpose of describing particular embodiments only, and is not intended to limit the present disclosure. As used in this disclosure and the appended claims, the singular...
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The invention provides a semiconductor module substrate and a design method. The semiconductor module substrate comprises a power metal coating layer group, an auxiliary metal coating layer group and a chip group, the power metal coating layer group comprises a first power metal coating layer, a second power metal coating layer, a third power metal coating layer and a fourth power metal coating layer; the auxiliary metal coating layer group comprises a first auxiliary metal coating layer, a second auxiliary metal coating layer, a third auxiliary metal coating layer, a fourth auxiliary metal coating layer and a fifth auxiliary metal coating layer; the chip group comprises a first chip array, a second chip array, a third chip array and a fourth chip array. After the technical scheme is adopted, on the premise that the reliability of the semiconductor module with the corresponding semiconductor module substrate is guaranteed, the rated current of the module is improved, and other indexes such as the power size, the power density and the working efficiency of the motor controller with the semiconductor module are increased.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor module substrate and a design method. Background technique [0002] With the increasing requirements of new energy vehicle manufacturers for the power level of motor controllers, the requirements for the current level of vehicle-level power modules are gradually increasing, and there is a need to increase the number of parallel connections of multi-chips inside the module to increase the rated current of the module. method. However, the increase in the number of parallel connections makes the steady-state and dynamic current sharing analysis of each chip branch more complicated, and the problem of series heat between chips is more serious, resulting in inconsistent junction temperatures of each chip and lower thermal reliability. At the same time, it is more difficult to suppress the stray inductance of the common source of the gate-level drive circuit of ...
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IPC IPC(8): H01L23/488H01L23/49H02P29/00
CPCH01L23/488H01L23/49H02P29/00H01L2224/49111H01L2224/48139
Inventor 沈捷周宇夏雨昕王明阳李一粟
Owner LEADRIVE TECH (SHANGHAI) CO LTD