Unlock instant, AI-driven research and patent intelligence for your innovation.

A system and method for reading and writing compatible two-dimensional structured data

A technology of data reading and writing and two-dimensional structure, applied in the field of data processing, can solve problems such as slowing down the actual operation of the system and processing efficiency, and achieve the effects of improving hit rate, accelerating throughput, and improving operation efficiency

Active Publication Date: 2022-03-01
NANJING SEMIDRIVE TECH CO LTD
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For data sources that exist in peripheral memory (DDR external memory, etc.) in two-dimensional form, such as digital images, sensor acquisition data, and neural network data stored in a similar form that can be equivalent to a large matrix, the algorithm logic often needs to be obtained one by one. A square area with m rows and n columns (or vector form, which can be regarded as the distortion of a matrix) of a two-dimensional data file or a two-dimensional graphic area of ​​other shapes is used for scientific operations such as convolution operations and iterative operations, while This kind of unit area with multiple consecutive calculations has a certain spatial and time domain continuity that is displaced from the center point of the area to the surroundings, so the unit area will have considerable overlap between consecutive multiple operations (such as figure 1 ), intuitively, this requires that when reading data from external memory to refresh the cache, the overlapping part should be kept in the cache as long as possible, and the unit area can be acquired by the operation processing unit faster, otherwise it will slow down the system Actual operation and processing efficiency

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A system and method for reading and writing compatible two-dimensional structured data
  • A system and method for reading and writing compatible two-dimensional structured data
  • A system and method for reading and writing compatible two-dimensional structured data

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0055] figure 2 It is a schematic diagram of a compatible two-dimensional structure data reading and writing system according to the present invention, such as figure 2 As shown, the compatible two-dimensional structured data reading and writing system of the present invention includes arithmetic execution processing unit (arithmetic execution unit) 201, random access memory selection unit (SRAM RW arbiter) 202, DMA unit 203, and prediction buffer unit (Prediction buffer) 204 , write strategy unit (write strategy) 205, Cache tag cache unit (Cache TAG buffer) 206, Cache preload unit (Cache preload) 207, and prefetch unit (prefetch) 208, wherein,

[0056] An arithmetic execution unit (arithmetic execution unit) 201 executes arithmetic instructions to read two-dimensional structure data from the predictive cache unit 204 to perform calculations, and sends the calculation results to the write strategy unit 205 .

[0057] The random memory selection unit (SRAM RW arbiter) 202 es...

Embodiment 2

[0066] Figure 4 For the flow chart of the method for reading and writing compatible two-dimensional structured data according to the present invention, reference will be made below Figure 4 , the method for reading and writing compatible two-dimensional structured data of the present invention is described in detail.

[0067] First, in step 401, the mapping structure of the Cache is determined, and the two-dimensional data is cache-mapped.

[0068] like figure 1 As shown, a data file in the system memory can be divided in a two-dimensional manner. Each line occupies a fixed number of bytes (bytes), which is recorded as stride, and the number of lines is recorded as lines. The dotted line is divided into squares, squares The width and height are tile_hsize and tile_vsize respectively. The physical address of the data file is file_addr, and the file size is file_size. The above parameters can be set as Cache registers. Register configurable values ​​can be as follows:

...

Embodiment 3

[0097] The present invention also provides a compatible two-dimensional structure data reading and writing chip, including the above-mentioned compatible two-dimensional structure data reading and writing system, which efficiently loads the operation data into the cache, maximizes the use of the bandwidth for accessing external memory, and improves the access of the operation unit. The hit rate of the cache speeds up the throughput of the computing unit to obtain data, thereby making full use of the computing resources in the digital logic system of the chip, and at the same time making full use of the actual physical device SRAM resources of the Cache, which is compatible with the general n-way combination mapping (n-way set-associative mapping) way. .

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A compatible two-dimensional structure data reading and writing system, comprising: a random access memory selection unit, which reads and writes SRAM according to the reading and writing requirements of the instruction decoding of the operation execution unit; a predictive cache unit, which predicts the two-dimensional data required for instruction execution Cache; write strategy unit, it is used to formulate the strategy that data is written into SRAM and writes back external storage; Cache tag cache unit, it caches the valid mark of Cache, the state value of square; Cache preload unit, it according to described Cache marks the update flag of the cache unit, generates a corresponding block refresh request, and puts it into the DMA unit request queue to update the Cache; the pre-read unit analyzes the computing tasks according to the preset batch, and marks the tasks . The system of the invention greatly improves the computing efficiency of the system with vector processing capability.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a system and method for reading and writing compatible two-dimensional structure data. Background technique [0002] In the digital logic system, in order to balance the relationship between the access of the slower storage unit and the high-speed operation processing unit, it is often necessary to introduce a Cache (caching) design. For data sources that exist in peripheral memory (DDR external memory, etc.) in two-dimensional form, such as digital images, sensor acquisition data, and neural network data stored in a similar form that can be equivalent to a large matrix, the algorithm logic often needs to be obtained one by one. A square area with m rows and n columns (or vector form, which can be regarded as the distortion of a matrix) of a two-dimensional data file or a two-dimensional graphic area of ​​other shapes is used for scientific operations such as convolution ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0862G06F12/0864G06F12/0804
CPCG06F12/0862G06F12/0864G06F12/0804G06F2212/1021G06F2212/1016G06F2212/1028
Inventor 李鹏张力航
Owner NANJING SEMIDRIVE TECH CO LTD