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Burst Clock Control Based on Local Command Decoding in Memory Devices

一种存储器、内部时钟的技术，应用在静态存储器、数字存储器信息、信息存储等方向，能够解决降低存储器装置总电力效率、消耗、多电力等问题

Active Publication Date: 2022-05-17
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since many commands may not require the burst clock, leaving the burst clock running may consume more power than would be useful for executing non-burst commands, thereby reducing the overall power efficiency of the memory device

Method used

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  • Burst Clock Control Based on Local Command Decoding in Memory Devices
  • Burst Clock Control Based on Local Command Decoding in Memory Devices
  • Burst Clock Control Based on Local Command Decoding in Memory Devices

Examples

Experimental program
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Embodiment Construction

[0013] One or more specific embodiments are described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be understood that in the development of any such practical implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as alignment with system-related and business-related constraints properties, which may vary from one embodiment to another. Furthermore, it should be understood that such a development effort might be complex and time consuming, but would nevertheless be a routine of design, construction, and fabrication to be undertaken by those skilled in the art having the benefit of this disclosure.

[0014] As previously mentioned, memory devices may use certain signals, such as chip select (CS) signals, to wake up certain aspects of the memory device, such ...

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PUM

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Abstract

The present disclosure relates to burst clock control based on partial command decoding in memory devices. The devices and methods include a command input configured to receive commands for a memory device. The second stage wakes up circuitry configured to receive a portion of the command and output an indication of whether the command is a non-burst command based on the portion. Clock gating circuitry is configured to receive an input clock and a wakeup signal. The clock gating circuitry is also configured to output an internal clock based at least in part on the received pulse of the wakeup signal. The clock gating circuitry is further configured to maintain the output of the internal clock for a duration based on the indication, wherein the duration is shorter when the indication indicates that the command is a non-burst command. short.

Description

technical field [0001] Embodiments of the present disclosure relate generally to the field of memory devices. More specifically, embodiments of the present disclosure relate to using a portion of a command to control a burst clock for a memory device. Background technique [0002] When a wake-up signal, such as a chip select (CS) signal, is received at the memory device, the memory device may wake up the command burst clock. The memory device may keep the command burst clock running until a sustain signal is fed back from the command / control logic region. However, due to various factors, this hold signal may take a relatively long time to return. For example, the command may span multiple cycles, causing delays in the propagation and decoding of the entire command. Additionally, various modes such as kickdown or power-down modes can complicate decoding. The memory device cannot distinguish between burst commands that utilize a burst clock, such as various types of read (...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/22
CPCG11C7/222G11C7/225G06F13/28G11C11/4076G11C7/1018G11C2207/2227G06F1/08G06F1/12G11C7/1039
Inventor K·马组德尔宫本尚幸
Owner MICRON TECH INC