Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, a gate structure and a side wall located on the side part of the gate structure, and the top of the side wall is higher than the top of the gate structure. The semiconductor structure further comprises a drain-source located in the substrate on the two sides of the gate structure, a conductive layer, a protection layer, a covering layer, a dielectric layer, a first interconnection layer and a second interconnection layer; the top of the drain-source is higher than or flush with the top of the substrate; the conductive layer is located on the drain-source; the protection layer is located at the top of the gate structure and located between the side walls, and the top surface of the protection layer is higher than the top surfaces of the side walls; the covering layer is located at the tops of the conductive layer and the side walls, and the top of the covering layer is flush with the top of the protection layer; the dielectric layer is located on the protection layer and the covering layer; the first interconnection layer is located in the protection layer at the top of the gate structure; and the second interconnection layer is located in the covering layer on the top of the conductive layer. According to the semiconductor structure provided by the embodiment of the invention, the problem of short circuit between the first interconnection layer and the conductive layer and between the second interconnection layer and the gate structure is avoided, and the electrical performance and the stability of the semiconductor structure are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] The scaling of feature sizes in integrated circuits has been the driving force behind the growing semiconductor industry over the past few decades. Scaling to smaller and smaller feature sizes enables an increased density of functional units on the limited real estate of a semiconductor chip. For example, reducing transistor size allows for an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the drive to greater capacity is not without its problems. The need to optimize the performance of each device is becoming increasingly apparent. [0003] In the manufacture of integrated circuit devices, such as multi-gate transistors, are becoming more common as device dimensions continue to sh...

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Problems solved by technology

[0004] But shrinking the size of multi-gate transistors is not without its consequences. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the number of building blocks used to form them increases. The constraints of the patterning lithography process become difficult to overcome

The electrical performance of multi-gate transistors in the prior art still needs to be improved

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