System, method, device and processor for realizing large-scale FIFO data processing based on DDR, and storage medium thereof

A data processing, DDR4AXI technology, applied in the direction of electrical digital data processing, memory systems, instruments, etc., can solve the problems of not being able to make full use of the high-speed DDR interface bandwidth, long data transmission time, and large effective transmission time to meet the requirements of modular design demand, ensure continuous data collection, and improve the effect of time utilization

Pending Publication Date: 2022-02-25
TRANSCOM INSTR
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Problems solved by technology

The process of this method is clear, but the effective transmission time is relatively long, the comprehensive bandwidth is not hig

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  • System, method, device and processor for realizing large-scale FIFO data processing based on DDR, and storage medium thereof
  • System, method, device and processor for realizing large-scale FIFO data processing based on DDR, and storage medium thereof
  • System, method, device and processor for realizing large-scale FIFO data processing based on DDR, and storage medium thereof

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[0038] In order to be more clearly described, further description is made in conjunction with specific embodiments.

[0039] The DDR-based system-based system of the present invention implements a large-scale FIFO data, including:

[0040] The entry asynchronous clock domain FIFO, has a separate write clock and read clock, independently sets the write data bit wide and read data bit wide, performing data writing operations;

[0041] The burst read and write data block is connected to the inlet asynchronous clock domain FIFO, and the data block list and the read data block list are written to the data block chain, and read the data block list.

[0042] The DDR4 AXI interface is connected to the burst read and write data block linked list for interaction with the flow control state machine and the burst reading.

[0043]Export asynchronous clock domain FIFO, is connected to the burst read and write data block linked table, configured to have a separate write clock and read clock, in...

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Abstract

The invention relates to a system for realizing large-scale FIFO (First In First Out) data processing based on DDR (Double Data Rate). The system comprises an inlet asynchronous clock domain FIFO; a sudden reading and writing data block linked list used for writing the data block linked list and reading the data block linked list by setting the data bit width and the data block length; a DDR4AXI interface which interacts with a flow control state machine and the sudden reading and writing data block linked list; an outlet asynchronous clock domain FIFO; and the flow control state machine which is used for data flow control and monitoring writing and reading of data flows of the inlet asynchronous clock domain FIFO, the DDR4AXI interface and the outlet asynchronous clock domain FIFO. The invention further relates to a method for achieving large-scale FIFO data processing based on the DDR through the DDR. By adopting the system, the method, the device, the processor for realizing large-scale FIFO data processing based on the DDR, and the computer readable storage medium, the time utilization rate is improved, the data acquisition efficiency is effectively improved, the FIFO storage depth is increased, and long-time continuous data acquisition is ensured.

Description

technical field [0001] The present invention relates to the field of wireless communication testing, in particular to the field of ultra-wideband wireless communication signal acquisition and analysis, and specifically refers to a system, method, device, processor and computer-readable storage medium for realizing large-scale FIFO data processing based on DDR. Background technique [0002] Wireless communication testing generally involves vector analysis and protocol analysis. The signal analyzer has the ability to collect and store time-domain signals for a certain period of time, so as to meet the subsequent signal analysis functions. The wireless communication RF signal analyzer has a frequency mixing architecture, which can convert the broadband RF signal to a lower frequency such as intermediate frequency or baseband. The intermediate frequency or analog baseband signal is sampled by a high-speed ADC to form quantized data, which is transmitted to the FPGA through a high...

Claims

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Application Information

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IPC IPC(8): G06F12/0879G06F12/0895G06F12/126
CPCG06F12/0879G06F12/0895G06F12/126G06F2212/1024G06F2212/1044G06F2212/1004G06F2212/1012
Inventor 李广兴沈伟豪
Owner TRANSCOM INSTR
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