IGBT device and manufacturing method thereof
A device and conductivity type technology, applied in the field of power semiconductor devices, can solve problems such as gate charging displacement current, and achieve the effect of EMI noise suppression and enhanced controllability
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Embodiment 1
[0035] Please refer to figure 1 , the present embodiment provides an IGBT device, which includes at least one cell, the cell includes a first electrode 1, a second electrode 2, and a semiconductor unit located between the first electrode 1 and the second electrode 2, and the semiconductor unit may include Base region 3 , source region 4 , drift region 5 , collector region 6 , trench gate structure 7 and PN junction structure 8 . The following description will be made by taking the IGBT device as an N-channel enhancement type as an example.
[0036] exist figure 1 In the illustrated embodiment, the first electrode 1 corresponds to the emitter electrode, covering the first surface (such as the upper surface) of the device, and the second electrode 2 corresponds to the collector electrode, covering the second surface (such as the lower surface) of the device. surface).
[0037] The base region 3 has the first conductivity type, for example, the base region 3 is a P-type base r...
Embodiment 2
[0061] In the following, description will be made by taking the IGBT device as an N-channel IGBT device as an example. In an embodiment, the first conductivity type is P type, and the second conductivity type is N type.
[0062] Please refer to Figure 4 , the present embodiment provides a method for manufacturing an IGBT device, comprising:
[0063] Step 1: Provide a substrate, the substrate includes a collector region 6, a buffer layer 9, a drift region 5 and a base region 3 stacked from bottom to top, or the substrate includes a collector region 6 stacked from bottom to top, a drift Region 5 and Base Region 3.
[0064] Such as Figure 5 As shown, the above collector region 6, buffer layer 9, drift region 5 and base region 3 can be formed by any existing method. For example, a single crystal silicon substrate is provided, and the substrate is heavily doped with P type to obtain a P+ collector region 6, and a buffer layer 9 or a drift layer is epitaxially formed on the up...
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