Transmission circuit, interface circuit and memory

Abstract

The embodiment of the invention provides a transmission circuit, an interface circuit and a memory, and the transmission circuit comprises an upper-layer clock bonding pad which is used for transmitting a clock signal; the M upper-layer data bonding pads are used for transmitting data signals; the lower-layer clock bonding pad is electrically connected with the upper-layer clock bonding pad, and the area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; the M lower-layer data bonding pads are electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence manner, and the area of the lower-layer data bonding pads is smaller than that of the upper-layer data bonding pads; the upper-layer clock bonding pad and the upper-layer data bonding pad are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pad are located on a second layer, a dielectric layer is arranged between the first layer and the second layer, and the first layer, the dielectric layer and the second layer are all located on the same substrate. According to the embodiment of the invention, the length of the clock path corresponding to each input buffer circuit is shortened, the time sequence violation is reduced, and the matching degree of the clock path corresponding to each input buffer circuit and the input data path is improved.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductors, and in particular, to a transmission circuit, an interface circuit, and a memory. Background technique [0002] Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage. [0003] DRAM can be divided into Double Data Rate (DDR) DRAM, GDDR (Graphics Double Data Rate) DRAM, and Low Power Double Data R...

AI Technical Summary

Problems solved by technology

[0004] However, current DRAM performance still needs to be improved

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