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Method for accelerating erasure of sub-blocks in 3D NAND flash memory

A sub-block and flash memory technology, which is applied in the field of accelerating sub-block erasure in 3D NAND flash memory, can solve the problems of impairing flash I/O performance, speeding up, and shortening the execution process of garbage collection, so as to reduce I/O blocking and shorten execution process, the effect of improving garbage collection performance

Pending Publication Date: 2022-03-04
XIAMEN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The purpose of the present invention is to solve the problems such as the serious large block problem that occurs in the 3D flash memory in the prior art that causes damage to the overall I / O performance of the flash memory, and to provide further reduction of effective page migration on the basis of the existing sub-block erasing A method of accelerating sub-block erasing in 3D NAND flash memory to shorten the execution process of garbage collection and alleviate I / O blocking conditions

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  • Method for accelerating erasure of sub-blocks in 3D NAND flash memory
  • Method for accelerating erasure of sub-blocks in 3D NAND flash memory
  • Method for accelerating erasure of sub-blocks in 3D NAND flash memory

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Embodiment Construction

[0036] The present invention will be further described below in conjunction with the accompanying drawings.

[0037] Embodiments of the present invention include the following steps:

[0038] Step 1: logical page heat division and data writing, the specific steps are:

[0039] 1.1 According to the access frequency of logical pages requested from the host in a short period of time, select multiple appropriate thresholds to distinguish logical pages with different write temperatures;

[0040] 1.2 According to the recovery benefits of each block, divide all blocks into different groups, the number of groups is the same as the total number of data heat, and concentrate the blocks with high recovery benefits; the calculation of block recovery benefits has different methods different, for example, the number of invalid sub-blocks in a block or the space released per unit time during garbage collection;

[0041] 1.3 By recording the temperature of each logical page, write the logic...

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Abstract

The invention discloses a method for accelerating erasing of sub-blocks in a 3D NAND flash memory, and relates to data processing. The method comprises the following steps: 1) data writing: dividing logic page popularity, and writing data with different popularity into blocks of different groups in a stepped manner; 2) garbage collection, including selection of a target block, selection of a target sub-block and migration of an effective page; and 3) based on mode design, determining a measurement index under different sub-block division modes, and writing data into the high-recovery-benefit sub-blocks. Different popularity of the data is distinguished, the data with different popularity is written into blocks in different groups in a stepped manner, and the number of invalid pages in the blocks is speculatively increased. According to the method, data access features are combined to a sub-block erasing method, workload features are applied to the design of sub-block erasing, and recovery of invalid pages in a flash memory is accelerated by writing high-heat data into sub-blocks to be recovered; the invalid pages in the flash memory can be more intensively distributed in a part of sub-blocks, and the garbage recycling benefit is greatly improved.

Description

technical field [0001] The present invention relates to data processing, in particular to a method for accelerating sub-block erasing in 3D NAND flash memory in combination with workload characteristics and inherent properties of 3D flash memory for solid-state hard drives based on 3D flash memory storage media. Background technique [0002] Fundamentally speaking, data storage in NAND flash memory is realized by retaining a certain number of electrons in the most basic storage unit-flash cells (R.Bez, E.Camerlenghi, A.Modelli, and A.Visconti.Introduction to flash memory. Proceedings of the IEEE, 91(4):489–502, 2003). There are three basic operations in flash memory: reading, writing and erasing, where reading and writing are performed in units of pages (a page is composed of multiple flash memory cells), and erasing operations are performed in blocks as a unit (each block contains multiple pages). Since the flash memory cells storing information cannot be rewritten again,...

Claims

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Application Information

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IPC IPC(8): G06F3/06
CPCG06F3/0604G06F3/064G06F3/0652G06F3/0679G06F12/0246G06F2212/7205
Inventor 沈志荣舒继武龚红彬
Owner XIAMEN UNIV