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FPGA BOX system and calculation method

A computing method and host system technology, applied in the computing field, can solve problems such as occupation, and achieve the effect of improving computing efficiency and saving PCIE slot resources

Inactive Publication Date: 2022-03-18
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the way of combining CPU with FPGA, it is necessary to insert FPGA into the PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) slot of the host computer to improve the computing power. When multiple FPGAs need to be inserted, it will seriously Occupies PCIE slot resources on the host

Method used

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  • FPGA BOX system and calculation method
  • FPGA BOX system and calculation method
  • FPGA BOX system and calculation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0042] refer to figure 1 as shown, figure 1 It is the first method flowchart of the calculation method of the FPGA BOX system of the present invention.

[0043] The computing method of the FPGA BOX system of the present embodiment comprises the following steps:

[0044] S1, the host system initiates a calculation operation and prepares the source data to be calculated;

[0045] In the way of combining CPU with FPGA, the CPU needs to issue instruction information to assign calculation tasks to the FPGA card device, and to realize the calculation through the FPGA card device, the source data to be calculated must first be prepared so that the source data to be calculated can be sent to the FPGA The card device, the source data is stored in the host memory module.

[0046] S2, the host system distributes computing tasks to one or more FPGA card devices among the plurality of FPGA card devices according to computing requirements;

[0047] The FPGA BOX system is used to store m...

Embodiment 2

[0081] refer to figure 2 as shown, figure 2 It is the second method flowchart of the calculation method of the FPGA BOX system of the present invention.

[0082] The computing method of the FPGA BOX system of the present embodiment comprises the following steps:

[0083] S10, the host system initiates a calculation operation, and prepares source data to be calculated;

[0084] In the way of combining CPU with FPGA, the CPU needs to issue instruction information to assign calculation tasks to the FPGA card device, and to realize the calculation through the FPGA card device, the source data to be calculated must first be prepared so that the source data to be calculated can be sent to the FPGA card device.

[0085] S20, analyzing the memory occupied by the source data to be calculated;

[0086] When calculation is required, the calculation task must first be analyzed. If the calculation task can be realized only by the CPU and / or GPU of the host system, there is no need to...

Embodiment 3

[0102] refer to image 3 as shown, image 3 It is a system structure diagram of the FPGA BOX system of the present invention.

[0103] The FPGA BOX system of the present embodiment comprises a plurality of FPGA card devices, and the FPGA BOX system is provided with a plurality of PCIE slots, and the FPGA card device can be plugged on the PCIE slot; the FPGA card device includes a communication module, a control module and a computing module ; Wherein, the communication module adopts RDMA communication; the control module is used for parsing and receiving control information.

[0104]Various data calculations and controls are realized through the host system. When the data needs to be transmitted to the FPGA card device for calculation, the data to be calculated is transmitted to the FPGA card device through RDMA, so that the data transmission does not pass through the CPU memory of the host system. The relay can be transmitted to the FPGA card device, so the number of data d...

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Abstract

The invention relates to an FPGA (Field Programmable Gate Array) BOX system and a calculation method, the FPGA BOX system is composed of a power supply device and an FPGA card device, a plurality of PCIE (Peripheral Component Interface Express) slots are formed in the FPGA BOX system, and the FPGA card device can be inserted into the PCIE slots; the FPGA card device comprises a communication module, a control module and a calculation module; wherein the communication module adopts RDMA (Remote Direct Memory Access) communication; and the control module is used for analyzing and receiving the control information. According to the FPGA BOX system and the calculation method, the multiple FPGA card devices are in communication connection with the host system through the RDMA, the multiple FPGA card devices are inserted into each FPGA BOX system, the host system controls the FPGA card devices on the FPGA BOX systems to conduct related data calculation, PCIE slot resources on the host system are saved, and the calculation efficiency is improved.

Description

technical field [0001] The present invention relates to the technical field of computing, in particular to an FPGA BOX system and a computing method. Background technique [0002] In mathematical calculations with very complex calculations, real-time calculations and other requirements are involved. In practical applications, the computing system is gradually optimized from the hardware in the form of CPU combined with FPGA (Field-Programmable Gate Array, Field-Programmable Gate Array). Significantly improve the overall computing power of the system. [0003] In the way of combining CPU with FPGA, it is necessary to insert FPGA into the PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) slot of the host computer to improve the computing power. When multiple FPGAs need to be inserted, it will seriously Occupies PCIE slot resources on the host. Contents of the invention [0004] In order to solve the above technical problems...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28G06F13/42G06F13/40G06F13/38
CPCG06F13/28G06F13/4221G06F13/4068G06F13/385
Inventor 刘伟宿栋栋沈艳梅阚宏伟
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD