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Low power consumption method for dense convolution operation core

A convolution operation, low power consumption technology, applied in the field of low power consumption algorithm optimization, to achieve the effect of reducing the frequency of data access, alleviating the problem of power wall, and improving the reuse rate

Pending Publication Date: 2022-03-22
JIANGNAN INST OF COMPUTING TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The power consumption wall is one of the problems faced by the CPU when it is running. Low power consumption is conducive to the stability of the chip and is also of great significance to saving energy. Especially, the issue of high power consumption poses a great challenge to the stable operation of the CPU.

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  • Low power consumption method for dense convolution operation core

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Embodiment

[0013] Embodiment: The present invention provides a low-power consumption method of dense convolution operation core, which specifically includes the following steps:

[0014] S1. Analyzing the characteristics of platform instructions, it is obtained that the data reuse rate of the instruction stream is high, that is, the data storage format P that can make the registers as reusable as possible;

[0015] S2. Determine whether the convolution input data is in the P storage format, and if so, jump to S4;

[0016] S3. Organize the convolution input data into a P storage format;

[0017] S4. At the instruction level, the calculation core of the P storage format is invoked through data reuse to perform calculations.

[0018] The further explanation to above-mentioned embodiment is as follows:

[0019] For high-power consumption topics such as convolution, when it is refined to the instruction level, floating-point operation instructions are executed almost every beat, and data ac...

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Abstract

The invention discloses a low-power-consumption method for a dense convolution operation core, and the method comprises the following steps: S1, analyzing platform instruction characteristics, and obtaining a data storage format P with high instruction stream data reuse; s2, judging whether the convolution input data is in a P storage format or not, and if yes, skipping to S3; s3, sorting the input data into a P storage format; and S4, calling the operation core in the P storage format for operation through data reuse at an instruction level. According to the method, the data access frequency of the storage component is remarkably reduced while the efficiency of the high-power-consumption project is not lost, so that the data access power consumption of the storage component is reduced, the CPU operation power consumption of the high-power-consumption project is remarkably reduced, the power consumption wall difficulty is relieved, and the energy consumption is reduced.

Description

technical field [0001] The invention relates to a low power consumption method for a dense convolution operation core, and belongs to the technical field of low power consumption algorithm optimization. Background technique [0002] Convolution is one of the most important concepts in deep learning. During the training and reasoning process of the convolutional neural network, the convolution operation occupies the vast majority of calculations. High-performance computing platforms usually provide specialized solutions. However, in terms of algorithm design, everyone is concerned about how to ensure the efficient implementation of convolution operations, and how to maintain low-power operation on the basis of efficient implementation is currently a blank. [0003] The operating power consumption of the CPU mainly comes from the flipping of the floating-point unit, the data access of the storage unit, and the operating consumption of other components. Among them, the invers...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/3234G06F7/483G06F17/15
CPCG06F1/3234G06F7/483G06F17/153
Inventor 林蓉芬袁欣辉尹万旺魏迪王飞孙浩男孙强史俊达
Owner JIANGNAN INST OF COMPUTING TECH