High-voltage LDMOS device and preparation method thereof
A device and high-voltage technology, applied in the field of high-voltage LDMOS devices and their preparation, can solve the problems of easy oxidation at high temperature, low crystal quality of deep trench isolation structure, etc., to improve the withstand voltage performance, improve reliability and yield, and achieve uniform thickness. good effect
Pending Publication Date: 2022-03-25
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
[0005] The application provides a high-voltage LDMOS device and its preparation method, which can solve the problem that the crystal quality of the deep trench isolation structure is not high, and when the deep trench isolation structure is prepared, the AA region in the substrate is easily oxidized by high temperature
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[0043] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.
[0044] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...
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The invention provides a preparation method of a high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device. The preparation method comprises the following steps: forming a first dielectric layer, a first silicon nitride layer, a second dielectric layer, a second silicon nitride layer and a third dielectric layer on a substrate; forming an isolation layer on the side surface and the bottom of the active region in the second groove by adopting a thermal oxidation furnace tube process; and filling a polycrystalline silicon inner core layer in the second trench to obtain the deep trench isolation structure. The invention further provides a high-voltage LDMOS device. The second dielectric layer, the second silicon nitride layer and the third dielectric layer are used as masks, and isolation layers with high crystal quality are formed on the side surface and the bottom of the active region in the second groove by adopting a thermal oxidation furnace tube process, so that the active region can be prevented from being mistakenly oxidized by high temperature, and the reliability and the yield of the device are improved. Furthermore, the isolation layer is formed in the second trench firstly, and then the residual space in the second trench is filled with the polycrystalline silicon inner core layer to obtain the deep trench isolation structure, so that the voltage resistance of the device can be improved.
Description
technical field [0001] The present application relates to the technical field of manufacturing high-voltage LDMOS devices, in particular to a high-voltage LDMOS device and a preparation method thereof. Background technique [0002] At present, high-voltage LDMOS is usually isolated by DTI (Deep Trench Isolation, deep trench isolation) structure to meet the withstand voltage requirements, and the filling method of DTI Trench is generally filled with pure silicon oxide dielectric layer, or partially thermal annealed oxidation Combination fill of silicon + partial poly. [0003] For the structure filled with pure silicon oxide dielectric layer, in order to facilitate groove filling, the silicon oxide dielectric layer is usually formed by CVD process, and the film quality of the silicon oxide dielectric layer prepared by CVD process is relatively poor, which will affect the performance of the device. Reliability; for the combined filling structure of partial thermal annealed si...
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IPC IPC(8): H01L21/762H01L21/763H01L29/78H01L21/336
CPCH01L21/76205H01L21/763H01L29/66681H01L29/7816
Inventor 朱兆强杨新杰金锋
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP