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Semiconductor device and forming method thereof

A technology of semiconductors and devices, applied in the field of semiconductor devices and their formation, can solve problems such as poor performance of LDMOS, and achieve the effects of expanding the scope of use, simplifying the process flow, and wide usability

Pending Publication Date: 2022-04-01
HUA HONG SEMICON WUXI LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the performance of existing LDMOS is poor

Method used

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  • Semiconductor device and forming method thereof
  • Semiconductor device and forming method thereof
  • Semiconductor device and forming method thereof

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Experimental program
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Embodiment Construction

[0026] The electrical performance of LDMOS in the prior art still needs to be improved. The following will describe in detail in conjunction with the accompanying drawings.

[0027] figure 1 is a schematic structural diagram of a semiconductor device in an embodiment.

[0028] Please refer to figure 1 Taking N-LDMOS as an example: P-type substrate / P-type epitaxial layer 101, shallow trench isolation (Shallow Trench Isolation, STI) 102 located in the P-type substrate / P-type epitaxial layer 101, located in the P-type The gate insulating dielectric layer 103 on the P-type substrate / P-type epitaxial layer 101, the gate polysilicon 104 on the gate insulating dielectric layer 103, the drift region located in the P-type substrate / P-type epitaxial layer 101 and The RESUR layer implant 105, the P-type body region implant 106 located in the drift region and the RESUR layer implant 105, the side wall dielectric layer 107 located in the gate insulating dielectric layer 103 and the side...

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Abstract

The invention discloses a semiconductor device and a forming method thereof, and the semiconductor device comprises a substrate which is internally provided with a drift region; a plurality of gate structures on the drift region, wherein each gate structure comprises a first side wall and a second side wall which are opposite to each other; the first side wall is positioned on the surface of the first side wall; the second side wall is positioned on the surface of the second side wall and is also positioned on the surface of a part of the drift region; the source-drain doped regions are respectively positioned on two sides of the gate structure, the first side wall and the second side wall; the second side wall located on a part of the surface of the drift region can be directly used as a field plate dielectric layer, and meanwhile metal of a contact hole formed subsequently is used as a field plate conductive electrode to be connected to a grid electrode or a source region of a source-drain doping region through a metal layer to form a field plate assisting in depletion of the drift region. And therefore, the same semiconductor device structure can also be applied to the Non-Salicide process. The technological process is simplified, the application range of the semiconductor device is expanded, and the semiconductor device has wide usability.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing toward higher component density, higher integration and higher performance. [0003] LDMOS (Laterally Diffused Metal Oxide Semiconductor, Laterally Diffused Metal Oxide Semiconductor) is a power device with a double diffusion structure. This technique is performed by implanting two ions into the substrate, one with a higher concentration of arsenic (As) and the other with a smaller concentration of boron (B). After implantation, a high-temperature annealing process is performed. Since boron diffuses faster than arsenic, it will diffuse farther along the lateral direction under the gate boundary to form a channel with a concentration gradient. Its channel length is determin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/40H01L29/78H01L21/336
Inventor 许昭昭
Owner HUA HONG SEMICON WUXI LTD