Wire end placement of top vias by selective growth of via mask from wire-cut dielectric

Abstract

Embodiments of the invention relate to a manufacturing method for placing a self-aligned top via (802) at a line end of an interconnect structure (100) and the resulting structure. In a non-limiting embodiment of the invention, a line feature (102) is formed in a metallization layer of an interconnect structure (100). The line features (102) may include a line hardmask (104). A trench (106) is formed in the line feature (102) to expose a line end of the line feature (102). The trench (106) is filled with a host material (202) and a growth inhibitor (402) is formed on the first line end of the line feature (102). A via mask (602) is formed on a second line end of the line feature (102). A via mask (602) may be selectively grown on an exposed surface of the host material (202). Portions of the line features (102) that are not covered by the via mask (602) are recessed to define self-aligned top vias (802) at the second line ends.

Description

technical field [0001] The present invention relates generally to methods of fabrication of semiconductor devices and resulting structures, and more particularly to fabrication for placing self-aligned top vias at line ends of interconnect structures by selectively growing via masks by cutting dielectric from the lines Methods and resulting structures. Background technique [0002] The fabrication of Very Large Scale Integration (VLSI) or Ultra Large Scale Integration (ULSI) circuits requires the fabrication of complex interconnect structures, including the metal wiring that connects the various devices in a semiconductor chip to each other. Typically, a routing interconnection network consists of two types of features that act as electrical conductors, namely, line features that span a distance across the chip, and via features that connect lines in different levels. The conductive metal lines and vias are made of conductive material, such as aluminum or copper, and are el...

AI Technical Summary

Problems solved by technology

As integrated circuit (IC) feature sizes continue to decrease, the aspect ratio (i.e., the ratio of height / depth to width) of features such as vias typically increases, complicating the manufacturing process

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