Wafer test result rigorous correction screening method
A technology of wafer testing and screening methods, applied in semiconductor/solid-state device testing/measurement, instrumentation, computing, etc., can solve the problem of high testing cost and achieve the effect of improving efficiency
Pending Publication Date: 2022-05-06
BEIJING TONGFANG MICROELECTRONICS
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Problems solved by technology
Although the detection degree of the test system can be improved by traversing the test temperature, test voltage, test vector and other conditions, the test cost required to do so is extremely high. A fast processing method for feature recognition and tightened correction screening to improve the efficiency of wafer testing
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[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0027] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0028] see figure 1 , the existing wafer test result map Map plan view. In the wafer test result map, the default chip 100 means that there is no chip in this area, the failed chip 200 means that the chip is a fa...
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According to the wafer test result rigorous correction screening method, Map tool software is used, feature recognition algorithm models of an edge failure chip, a continuous failure chip and an isolated effective chip are defined, and on the basis of pattern recognition of areas where the edge failure chip, the continuous failure chip and the isolated effective chip are located, the rigorous correction screening result is obtained. According to the method, effective chips passing wafer testing in the area can be corrected, so that wafer testing results on the boundary of the continuous failure chip area are subjected to strict correction and then are transposed and output, the wafer testing results are associated with the process, and potential failure chips are filtered; therefore, the efficiency of identifying the failed chip and the overall reliability of chip product output are improved.
Description
technical field [0001] The invention relates to the field of semiconductor product manufacturing, in particular to a method for tightening, revising and screening wafer test results. Background technique [0002] The production of integrated circuits takes several weeks, requires hundreds of independent processes, and will repeat dozens of core processes such as: cleaning, photoresist coating, exposure, development, etching, doping, annealing and other processes. In the current production process, the control and production of the process are carried out in batches of Lot (a group of wafers, wafers are Wafers). Usually, a Lot consists of 25 wafers. In some processes, the wafers in a Lot will be operated under the same equipment at the same time. [0003] Wafer testing (Chip Probing in English, CP for English abbreviation), also known as mid-testing, is a wafer-level screening test that performs a functional screening test on the wafer before chip reduction and packaging to ...
Claims
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IPC IPC(8): G06F30/392H01L21/66
CPCG06F30/392H01L22/20Y02P90/30
Inventor 欧阳睿肖金磊许秋林郭耀华陈凝马迁
Owner BEIJING TONGFANG MICROELECTRONICS