Chip, neural network processor and manufacturing method of chip
A neural network and processor technology, applied in the field of integrated circuits, can solve the problems of large clock delay of clock signals, different clock delays, and difficulty in data transmission meeting timing requirements, so as to reduce the difference and reduce the clock delay. effect when
Pending Publication Date: 2022-05-24
GUANGDONG OPPO MOBILE TELECOMM CORP LTD
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The above approach makes the clock delay of the clock signal larger, and the clock signal that needs to be transmitted to other functional modules has different clock delays in the control module, which makes it difficult for data transmission to meet the timing requirements
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[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments.
[0020] At present, among digital integrated circuits, synchronous integrated circuits (using a synchronous control method) are widely used due to their simple design and easy implementation of operation control. In a synchronous integrated circuit, the data transmission between the functional modules in the chip can be synchronously controlled through a clock signal.
[0021] In the related art, a clock signal may be provided and transmitted to each functional module in a chip through a clock network (eg, a clock tree). Taking the clock tree as an example, the clock tree refers to that after the clock signal is sent from the clock source, it is tr...
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The invention provides a chip, a neural network processor and a manufacturing method of the chip. The chip comprises a control module which comprises an input port, an output port and a clock network, the input port is used for receiving a first clock signal, and the clock network is used for transmitting the first clock signal to the output port; the synchronization module comprises a register, a clock port of the register is connected with the output port, and the first clock signal is transmitted to the clock port of the register through the output port, so that the synchronization module performs clock synchronization according to the first clock signal; wherein the clock network comprises a first common path, a first end of the first common path is connected with the input port, and a second end of the first common path directly reaches the output port. When the first clock signal enters the control module, the first clock signal directly reaches the output port of the control module through the first common path, so that the clock delay of the first clock signal is reduced, and the difference value between the clock delays of the first clock signal in the control module is reduced.
Description
technical field [0001] The present application relates to the field of integrated circuits, and more particularly, to a chip, a neural network processor and a method for manufacturing the chip. Background technique [0002] In a synchronous integrated circuit, the data transmission between each functional module in the chip can be synchronously controlled by a clock signal. When the traditional clock tree is used to transmit the clock signal, after the clock signal enters from the control module in the chip, it is transmitted to the clock ports of the registers of other functional modules through the clock tree of the control module. The above method makes the clock delay of the clock signal larger, and the clock delay of the clock signal to be transmitted to other functional modules varies in the control module, which makes it difficult for data transmission to meet the timing requirements. SUMMARY OF THE INVENTION [0003] In view of this, the present application provid...
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Login to View More IPC IPC(8): G06F1/12G06F1/04G06F9/30
CPCG06F1/12G06F9/30098G06F1/04Y02D10/00
Inventor 郭飞亚
Owner GUANGDONG OPPO MOBILE TELECOMM CORP LTD