Power consumption attack resistant storage unit based on digital mechanism

Abstract

The invention discloses an anti-power consumption attack memory cell based on a digital mechanism. The memory cell consists of a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a second PMOS transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, a second NMOS transistor, a first phase inverter, a second phase inverter, a third phase inverter, a first transmission gate and a second transmission gate. According to the power consumption attack resisting storage unit based on the digital mechanism, the side channel attack resisting capacity of the unit circuit can be improved, the stability of the unit can be greatly improved under the condition that a small unit area is sacrificed, and the power consumption of the unit is reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a digital mechanism-based anti-power consumption attack storage unit. Background technique [0002] Today, Side Channel Attack (SCA) has become a serious threat to security systems because it can extract confidential data by analyzing the current drawn by the power plane of the system. Static random access memory (SRAM), a key component of these security systems, is a prime target for attacks. like figure 1 As shown, a conventional SRAM cell consisting of 6 transistors (6T cell for short) proved to be vulnerable to side-channel attacks. When a traditional 6T cell is written, the power consumption of the write operation varies according to the data stored in the cell. The attacker obtains the original data information stored in the unit by analyzing the correlation between the write power consumption and the internal storage data. [0003] With the emergence ...

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Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a storage unit based on a digital mechanism that resists power consumption attacks, which is used to solve the problem of high power consumption and slow write speed in the static random storage unit in the prior art. Low, interfered by half-selected questions, and questions with low noise tolerance

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