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Semiconductor packaging structure and manufacturing method thereof

A packaging structure and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device parts, etc. Problems such as the area of ​​the package structure to achieve the best structural reliability, increase the bonding area, and improve the bonding strength.

Pending Publication Date: 2022-07-08
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the step-shaped wettable flanks are still limited in the area exposed to the package structure, and cannot greatly improve the bonding strength of the pins electrically connected to the printed circuit board.

Method used

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  • Semiconductor packaging structure and manufacturing method thereof
  • Semiconductor packaging structure and manufacturing method thereof
  • Semiconductor packaging structure and manufacturing method thereof

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Embodiment Construction

[0049] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

[0050] Exemplary embodiments of the present invention will be fully described below with reference to the accompanying drawings, but the present invention may also be embodied in various different ways and should not be construed as limited to the embodiments described herein. In the drawings, for the sake of clarity, the size and thickness of various regions, parts and layers may not be drawn to scale. In order to facilitate understanding, the same elements in the following description will be described with the same symbols.

[0051] 1A to 1G It is a schematic cross-sectional view of a method for fabricating a semiconductor package structure according to an embodiment of the present invent...

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PUM

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Abstract

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises a lead frame, a chip, a packaging colloid and a conductive material layer. The lead frame comprises a bearing seat and a plurality of pins. Each pin is provided with a top surface, a first bottom surface, an inner side end and an outer side end. The inner side end faces the bearing seat, and the outer side end is provided with a recess at the first bottom surface, so that the outer side end is connected with the top surface and the first bottom surface through the plane side wall and the arc-shaped recess surface. The chip is arranged on the bearing seat and is electrically connected with the pins. The packaging colloid covers the lead frame and the chip. The encapsulant has a lower surface and a side surface. The lower surface is exposed and aligned with the first bottom surface of the pin. The side surface is flush with the plane side wall of the pin and exposes the surface of the arc-shaped recess. The conductive material layer is disposed on the first bottom surface of the pin and the surface of the arc-shaped recess. According to the semiconductor packaging structure and the manufacturing method thereof, the pins have better bonding strength.

Description

technical field [0001] The present invention relates to a semiconductor packaging structure, in particular to a semiconductor packaging structure and a manufacturing method thereof. Background technique [0002] In recent years, in order to achieve miniaturized packages, the dual flat no-lead (DFN) package structure and the quad flat no-lead (QFN) package structure with a small package area are just like Become the mainstream in the current packaging process. Due to the small package size and excellent heat dissipation, quality stability and electrical functions of the two-side flat no-lead and four-side flat no-lead packages, they have been widely used in various types of packaging structures. [0003] In general, the 2-side flat no-lead package and the 4-side flat no-lead package only use the exposed bottom surface of the lead as the external electrical connection point. Under such circumstances, the limited wettable area often cannot provide sufficient bonding strength ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/49H01L23/495H01L21/56
CPCH01L23/3121H01L23/49H01L23/49544H01L21/56H01L2224/97H01L2224/32245H01L2924/181H01L2224/73265H01L2224/48247H01L2224/48091H01L2924/00012H01L2924/00014H01L2924/00
Inventor 周世文
Owner CHIPMOS TECH INC