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Silicon passivation-based p-GaN gate enhanced MIS-HEMT device and preparation method thereof

A kind of MIS-HEMT, enhanced technology, applied in p-GaN gate enhanced MIS-HEMT device based on silicon passivation and its preparation field, can solve the problems of device threshold voltage drift, cut-off frequency reduction, device parameter degradation, etc. Achieve the effects of passivating surface states and defects, increasing output current, and improving withstand voltage

Pending Publication Date: 2022-07-22
XIDIAN UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The gate oxide layer of p-GaN gate-enhanced MIS (metal-insulator-semiconductor)-HEMT devices can effectively reduce the gate leakage current, but since the epitaxial growth process of GaN materials is carried out in a non-thermodynamic equilibrium state, the material surface A large number of defects and dangling bonds, the interface state between GaN and the oxide layer can capture or release electrons, causing problems such as device threshold voltage drift, gain reduction, and cut-off frequency reduction, resulting in device parameter degradation and reliability reduction, so p-GaN Gate-enhanced MIS-HEMT devices have not been commercialized

Method used

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  • Silicon passivation-based p-GaN gate enhanced MIS-HEMT device and preparation method thereof
  • Silicon passivation-based p-GaN gate enhanced MIS-HEMT device and preparation method thereof
  • Silicon passivation-based p-GaN gate enhanced MIS-HEMT device and preparation method thereof

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Embodiment 1

[0039] See figure 1 , figure 1 It is a schematic structural diagram of a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation provided by an embodiment of the present invention, and the p-GaN gate enhancement mode MIS-HEMT device includes a substrate layer 1 arranged in sequence from bottom to top , nucleation layer 2, buffer layer 3, channel layer 4 and barrier layer 5, isolation regions 7 are respectively opened on both sides of the barrier layer 5, and the isolation region 7 extends from the upper surface of the barrier layer 5 to the buffer layer 3 The upper surface of the upper surface of the barrier layer 5 is provided with a cap layer 6, a passivation layer 8, an oxide layer 9 and a gate electrode 10 in sequence from bottom to top in the middle position of the upper surface of the barrier layer 5, and active electrode 11 and drain electrode 12 .

[0040] In this embodiment, the material selected for the substrate layer 1 is Si, SiC or sapphire.

...

Embodiment 2

[0047] On the basis of the above embodiments, this embodiment provides a method for fabricating a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation. Please refer to figure 2 , Figures 3a to 3g , the preparation method includes:

[0048] S1: Select a substrate and sequentially grow a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer on the substrate.

[0049] Specifically, a Si, SiC or sapphire substrate 1 is selected, and plasma cleaning and surface pretreatment are performed on the surface of the substrate 1 to keep the substrate surface clean; then, metal organic chemical vapor deposition (MOCVD) is used. process, on the substrate sequentially grow an AlN nucleation layer 2 with a thickness of 50-500 nm, an AlGaN buffer layer 3 with a thickness of 200-8000 nm, a GaN channel layer 4 with a thickness of 50-500 nm, and a thickness of 10-30 nm Al x Ga 1-x N barrier layer 5, Mg-doped p-GaN cap layer 6 with a thickness ...

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Abstract

The invention discloses a silicon passivation-based p-GaN gate enhanced MIS-HEMT device and a preparation method thereof, the device comprises a substrate layer, a nucleating layer, a buffer layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, and isolation regions are respectively arranged on two sides of the barrier layer; the isolation region extends from the upper surface of the barrier layer to the upper surface of the buffer layer; a cap layer, a passivation layer, an oxide layer and a gate electrode are sequentially arranged in the middle of the upper surface of the barrier layer from bottom to top, and a source electrode and a drain electrode are arranged on the two sides of the upper surface of the barrier layer respectively. The passivation layer is deposited on the cap layer, so that the oxide layer and the barrier layer can be isolated, the surface state and defects of the p-GaN material are greatly passivated, the voltage resistance of the p-GaN grid is effectively improved, the threshold voltage drift of the device is improved, the output current is increased, and the leakage current of the grid is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, in particular to a p-GaN gate enhancement type MIS-HEMT device based on silicon passivation and a preparation method thereof. Background technique [0002] High Electron Mobility Transistor (HEMT) based on gallium nitride (GaN) has excellent performance of high electron mobility and high breakdown voltage due to the use of a conductive channel formed by a two-dimensional electron gas structure. Due to the wide band gap characteristics of GaN materials, GaN-based HEMT devices have good high temperature characteristics and radiation resistance characteristics, and are favored in harsh application environments such as high frequency, high voltage, and high power. [0003] The p-GaN gate enhancement mode HEMT device depletes the two-dimensional electron gas under the gate region through the built-in electric field generated by the p-GaN gate structure, and has high threshold voltage, sa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/778H01L23/31H01L21/56H01L21/335
CPCH01L29/7787H01L29/66462H01L23/3171H01L21/56
Inventor 李祥东王萌袁嘉惠张进成郝跃
Owner XIDIAN UNIV