Microelectronic devices and related memory devices, electronic systems, and methods

Abstract

The present application relates to microelectronic devices and related memory devices, electronic systems, and methods. A microelectronic device includes a stack structure including insulative structures vertically interleaved with conductive structures; first support pillar structures vertically extending through the stack structure in a first stair-step region, the first stair-step region including a step defined at an edge of a layer of the insulative and conductive structures; and second support pillar structures vertically extending through the stack structure in a second stair-step region, the second stair-step region including an additional step defined at an edge of an additional layer of the insulative and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

Description

[0001] Priority requirements

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 314,485, filed May 7, 2021, entitled “Microelectronic Devices Including Differently Sized Conductive Contact Structures, and Relatted Memory Devices, Electronic Systems, and Methods,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to microelectronic devices and apparatuses comprising a first conductive contact structure having dimensions different from those of a second conductive contact structure, and to related memory devices, electronic systems, and methods of forming microelectronic devices. Background Technology

[0004] A persistent goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in a stack of layers that pass through conductive structures (e.g., word lines) and dielectric material at each junction of the vertical memory strings and the conductive structures. Compared to a conventional planar (e.g., two-dimensional) arrangement with transistors, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by constructing the array upwards (e.g., longitudinally, vertically) on the die.

[0005] Conventional vertical memory arrays include electrical connections between conductive structures and access lines (e.g., word lines), allowing for the unique selection of memory cells within the vertical memory array for write, read, or erase operations. One method of forming such electrical connections involves forming at least one so-called "step" (or "staircase") structure at the edge (e.g., horizontal end) of a layer of conductive structure. The staircase structure includes individual "steps" providing contact areas for the conductive structure, on which conductive contact structures can be positioned to provide electrical access to the conductive structure.

[0006] With the development of vertical memory array technology, additional memory density has been provided by forming vertical memory arrays as stacks containing additional layers including conductive structures and thus additional step structures and / or additional steps in their associated individual step structures. As the height of the stack increases to facilitate additional memory cells in the vertical memory array, the stack can be prone to tipping or collapse during various processing actions. For example, during a gate replacement processing action, the stack may experience layer collapse during or after the removal of a portion of the layer to be replaced by the conductive structure to be used. Partial collapse of the stack can reduce the reliability of the vertical memory string. Summary of the Invention

[0007] In some embodiments, a microelectronic device includes: a stacked structure including insulating structures vertically intersecting with conductive structures; a first support pillar structure extending vertically through the stacked structure in a first stepped region, the first stepped region including steps defined at the edges of layers of the insulating and conductive structures; and a second support pillar structure extending vertically through the stacked structure in a second stepped region, the second stepped region including additional steps defined at the edges of additional layers of the insulating and conductive structures, each of the second support pillar structures having a smaller lateral cross-sectional area than each of the first support pillar structures.

[0008] In other embodiments, a memory device includes: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers; an array region comprising a string of memory cells extending vertically through the stacked structure; a first step region laterally adjacent to the array region and including steps defined at lateral edges of some of the layers of conductive and insulating structures; a second step region laterally adjacent to the first step region and including additional steps defined at lateral edges of the others of the layers of conductive and insulating structures; a first conductive contact structure electrically connected to the steps of the first step region; and a second conductive contact structure electrically connected to the additional steps of the second step region, the second conductive contact structure having a larger dimension than the first conductive contact structure.

[0009] In another embodiment, a method of forming a microelectronic device includes: forming pillars comprising channel material in an array region of a stacked structure, the stacked structure comprising a vertically alternating sequence of insulating structures and additional insulating structures; forming an insulating material vertically covering the pillars and vertically covering a distributed stepped region, the distributed stepped region comprising a first stepped region laterally adjacent to the array region and a second stepped region laterally adjacent to the first stepped region; forming a groove extending vertically through the stacked structure; replacing at least a portion of each of the additional insulating structures with a conductive structure through the groove; filling the groove with material to form a groove structure; forming an opening in the array region, each of the openings exposing conductive material electrically connected to one of the pillars; forming an additional opening in the first stepped region, each of the additional openings individually exposing one of the conductive structures; forming conductive material in the openings to form a conductive contact in the array region; and forming conductive material in the additional openings to form a first conductive contact structure in the first stepped region.

[0010] In another embodiment, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure. The at least one microelectronic device structure includes: an array region including a string of memory cells extending vertically through an alternating vertical sequence of insulating and conductive structures; and a first step region laterally adjacent to the array region and including first conductive contact structures extending vertically through a dielectric material overlying the first step region, each of the first conductive contact structures being individually electrically connected to one of the conductive structures. The conductive structure includes: a conductive liner material contacting the dielectric material; and a conductive material contacting the conductive liner material. The at least one microelectronic device structure further includes a second step region laterally adjacent to the first step region and including second conductive contact structures each having a larger dimension than each of the first conductive contact structures, the second conductive contact structures extending vertically through the dielectric material and being individually electrically connected to another of the conductive structures. Each of the second conductive contact structures includes: an oxide liner material in contact with the dielectric material; an additional conductive liner material in contact with the oxide liner material; and an additional conductive material in contact with the additional conductive liner material. Attached Figure Description

[0011] Figures 1A to 1O A simplified partial cross-sectional view illustrating a method for forming a microelectronic device structure according to embodiments of the present disclosure. Figure 1A , Figure 1C , Figure 1F , Figure 1I , Figure 1K and Figure 1N ) and simplified top view ( Figure 1B , Figure 1D , Figure 1E , Figure 1G , Figure 1H , Figure 1J , Figure 1L , Figure 1M and Figure 10 );

[0012] Figure 2 A partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure;

[0013] Figure 3 According to embodiments of this disclosure Figure 2 A simplified perspective view of the microelectronic device structure shown in the image;

[0014] Figure 4 This is a block diagram of an electronic system according to an embodiment of the present disclosure; and

[0015] Figure 5 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0016] The illustrations contained herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or its integrated circuit, but are merely idealized representations for describing the embodiments herein. Elements and features shared between the figures may retain the same numerical designations, but for ease of description below, the reference numerals begin with the designation of the figure on which the element is introduced or most fully described.

[0017] The following description provides specific details, such as material types, material thicknesses, and processing conditions, to provide a full description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the description provided herein does not constitute a complete process flow for manufacturing a microelectronic device (e.g., a semiconductor device, a memory device (e.g., a DRAM memory device)), apparatus, memory device, or electronic system, or a complete microelectronic device, apparatus, memory device, or electronic system comprising conductive structures (e.g., a select gate structure) exhibiting greater conductivity than other conductive structures. The structures described below do not form a complete microelectronic device, apparatus, memory device, or electronic system. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete microelectronic device, apparatus, memory device, or electronic system from the structures can be performed using conventional techniques.

[0018] Unless otherwise specified, the materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the material can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by one of ordinary skill in the art. Unless the context otherwise indicates, material removal can be achieved by any suitable technique including but not limited to etching, abrasive planarization (e.g., chemical mechanical planarization), or other known methods.

[0019] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to the principal plane of a substrate (e.g., substrate material, substrate structure, substrate configuration, etc.) on which one or more structures and / or features are formed and are not necessarily defined by the Earth’s gravitational field. A “lateral” or “horizontal” direction is a direction substantially parallel to the principal plane of the substrate, while a “longitudinal” or “vertical” direction is a direction substantially perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by a surface of the substrate that has a relatively large area compared to the other surfaces of the substrate.

[0020] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and includes the degree to which a given parameter, characteristic, or condition conforms to variance (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, characteristic, or condition that is substantially satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0021] As used herein, the term "about" or "approximately" with respect to a particular parameter includes the value, and those skilled in the art will understand that the deviation from the value is within acceptable tolerances for the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​within 90.0% to 110.0% of the value, such as within 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0022] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” and “right” may be used for ease of description to illustrate the relationship of one element or feature to another element(s) as shown in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is inverted, then an element described as “below,” “under,” “down,” or “on the bottom” of another element or feature would be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0023] As used herein, features described as “adjacent” to each other (e.g., area, material, structure, device) mean and include features that are most closely (e.g., closest to) positioned with respect to each other and are identified by a disclosed identifier (or multiple identifiers). Additional features (e.g., additional area, additional material, additional structure, additional device) that do not match the disclosed identifier (or multiple identifiers) of an “adjacent” feature may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other mean and include features that are most closely (e.g., closest to) vertically positioned with respect to each other and are identified by a disclosed identifier (or multiple identifiers). Furthermore, features described as “horizontally adjacent” to each other mean and include features that are most closely (e.g., closest to) horizontally positioned with respect to each other and are identified by a disclosed identifier (or multiple identifiers).

[0024] As used herein, the term "memory device" means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices with combinational logic and memory, and graphics processing units (GPUs) incorporating memory.

[0025] As used herein, “conductive material” means and includes one or more of the following conductive materials: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Fe-based alloys) The term "conductive structure" refers to and includes structures formed from and containing conductive materials. It encompasses gold, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co-Ni-Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel. It also includes conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), and conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed from and containing conductive materials.

[0026] As used herein, “insulating material” means and includes electrically insulating materials, such as at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y One or more of the chemical formulas “x”, “y”, and “z” are included in this document (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiOx N y SiO x C z N y A chemical formula represents a material containing “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if present) relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because a chemical formula represents relative atomic ratios rather than strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of “x,” “y,” and “z” (if present) can be integers or non-integers. As used herein, the term “non-stoichiometric compound” means and includes compounds composed of an element that cannot be expressed by a well-defined ratio of natural numbers and violates the law of definite proportions. Additionally, “insulating structure” means and includes structures formed from and containing insulating materials.

[0027] According to embodiments described herein, a microelectronic device includes a stacked structure comprising insulating structures that alternate vertically with conductive structures arranged in layers. The stacked structure may be divided into an array region comprising a string of memory cells extending vertically through the stacked structure and a stepped region comprising one or more stepped structures. Each of the stepped structures may include a step defined at a lateral edge of a layer of vertically alternating insulating and conductive structures. A first conductive contact structure may extend vertically through a dielectric material overlying the stepped region and may be electrically connected to some of the conductive structures at steps of at least a first stepped structure (e.g., a stepped structure defined by a conductive structure used as an upper select gate structure, e.g., a select gate drain (SGD) structure). A second conductive contact structure may extend vertically through the dielectric material and may be electrically connected to other conductive structures at steps of others in the stepped structure (e.g., second, third). The first conductive contact structure may have a lateral dimension (e.g., diameter) smaller than the lateral dimension (e.g., diameter) of the second conductive contact structure. The first conductive contact structure may have a lateral dimension (e.g., diameter) substantially the same as the lateral dimension (e.g., diameter) of the conductive contact element, which is in series communication with and couples the memory cell series to conductive lines (e.g., data lines, such as bit lines). In some embodiments, the first conductive contact structure includes a conductive contact structure for selecting a gate structure (such as an SGD structure). In some embodiments, the first and second conductive contact structures comprise a conductive liner material (e.g., a conductive metal nitride liner material). In some embodiments, the second conductive contact structure further comprises an oxide liner material, and the first conductive contact structure does not comprise an oxide liner material.

[0028] Additionally, the first support pillar structure extends vertically through the stacked structure within at least the first step region, and the second support pillar structure extends vertically through the stacked structure within other step structures. The first support pillar structure may have a lateral dimension (e.g., diameter, length, width) larger than that of the second support pillar structure. The smaller lateral dimension of the first conductive contact structure relative to the second conductive contact structure contributes to the larger lateral dimension of the first support pillar structure relative to the second support pillar structure. The larger lateral dimension of the first support pillar structure relative to the second support pillar structure helps reduce the likelihood of layer collapse of the insulating structure (e.g., within at least the first step region) during so-called "gate replacement" or "gate persistence" processing operations.

[0029] Figures 1A to 1O A method for forming a microelectronic device structure according to embodiments of the present disclosure is described. Figure 1A This is a simplified cross-sectional view of the microelectronic device structure 100. Figure 1B For crossing Figure 1A The simplified top view of the microelectronic device structure 100 is taken by section line BB. The microelectronic device structure 100 may be formed, for example, as part of a memory device (e.g., a multi-stack 3D NAND flash memory device, such as a dual-stack 3D NAND flash memory device), as described in further detail below.

[0030] refer to Figure 1A The microelectronic device structure 100 includes a stacked structure 102 comprising a vertically alternating (e.g., in the Z direction) sequence of insulating structures 104 and additional insulating structures 106 arranged in layers 108. Each of the layers 108 of the stacked structure 102 may include at least one (1) of the insulating structures 104 that are vertically adjacent to at least one (1) of the additional insulating structures 106.

[0031] The insulating structure 104 may be individually formed of and comprise an insulating material, such as an oxide material (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), tantalum oxide (TaO2), magnesium oxide (MgO), aluminum oxide (Al2O3), or combinations thereof) and amorphous carbon, or one or more thereof. In some embodiments, the insulating structure 104 comprises silicon dioxide. Each of the insulating structures 104 may individually comprise at least one insulating material that is substantially uniformly distributed or substantially nonuniformly distributed. As used herein, the term “uniformly distributed” means that the amount of material does not change throughout the different parts of the structure (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term “nonuniformly distributed” means that the amount of material varies throughout the different parts of the structure. The amount of material can vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) throughout different parts of the structure. In some embodiments, each of the insulating structures 104 of each of the layers 108 of the stacked structure 102 exhibits a substantially uniformly distributed insulating material. In additional embodiments, at least one of the insulating structures 104 of at least one of the layers 108 of the stacked structure 102 exhibits a substantially non-uniformly distributed at least one insulating material. The insulating structure 104 may be formed (e.g., laminated) and comprise, for example, a stack of at least two different insulating materials. The insulating structures 104 of each of the layers 108 of the stacked structure 102 may each be substantially planar and may each individually exhibit the desired thickness.

[0032] The layers of the additional insulating structure 106 may be formed and comprise an insulating material that is different from and exhibits etch selectivity with respect to the insulating structure 104. In some embodiments, the additional insulating structure 106 is formed and comprises one or more of the following: nitride materials (e.g., silicon nitride (Si3N4)) or oxide nitride materials (e.g., silicon oxynitride). In some embodiments, the additional insulating structure 106 comprises Si3N4.

[0033] although Figure 1AThe present disclosure describes a specific number of layers 108 of insulating structure 104 and additional insulating structure 106, but is not limited thereto. In some embodiments, stack structure 102 includes a desired number of layers 108, for example, in the range of thirty-two (32) layers 108 to two hundred and fifty-six (256) layers 108. In some embodiments, stack structure 102 includes sixty-four (64) layers 108. In other embodiments, the stack structure 102 includes different numbers of layers 108 of insulating structure 104 and additional insulating structure 106, such as less than sixty-four (64) layers 108 (e.g., less than or equal to sixty (60) layers 108, less than or equal to fifty (50) layers 108, less than about forty (40) layers 108, less than or equal to thirty (30) layers 108, less than or equal to twenty (20) layers 108, less than or equal to ten (10) layers 108); or more than sixty-four (64) layers 108 (e.g., more than or equal to seventy (70) layers 108, more than or equal to one hundred (100) layers 108, more than or equal to about one hundred and twenty-eight (128) layers 108, more than two hundred and fifty-six (256) layers 108). Additionally, in some embodiments, the stacked structure 102 is covered by an additional layer 108 comprising an insulating structure 104 and an additional insulating structure, the stacked structure being separated from the stacked structure 102 by at least one dielectric material such as an inter-stack insulating material.

[0034] Continue to refer to Figure 1A The microelectronic device structure 100 further includes a source layer 110 vertically resting (e.g., in the Z direction) on the stacked structure 102. The source layer 110 may include, for example, a first source material 112 and a second source material 114. The first source material 112 may be formed of at least one conductive material and may include at least one conductive material, such as metals (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys), conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and doped semiconductor materials (polycrystalline silicon doped with one or more P-type dopants, such as one or more of boron, aluminum, and gallium; polycrystalline silicon doped with one or more N-type conductive materials, such as one or more of arsenic, phosphorus, antimony, and bismuth). In some embodiments, the first source material 112 comprises conductive doped silicon.

[0035] The second source material 114 may be formed from one or more of the following and includes one or more of the following: metal silicide materials (e.g., tungsten silicide (WSi)). x Metal nitride materials (e.g., tungsten nitride) and silicon nitride materials (e.g., silicon tungsten nitride (WSi)). x N y In some embodiments, the second source material 114 comprises tungsten silicide.

[0036] The microelectronic device structure 100 may include an array region 105 and a distributed stepped region 115 laterally adjacent (e.g., in the Y direction) to the array region 105. As will be described herein, the array region 105 may include vertical (e.g., in the Z direction) memory cells (e.g., memory cell 174) extending vertically through the stacked structure 102. Figure 1I )) of strings (e.g., string 172) Figure 1I )).

[0037] The distributed step area 115 may include one or more step areas, such as at least a first step area 115a, a second step area 115b, and a third step area 115c. The first step area 115a may be a lateral (e.g., in the Y direction) terminal step area of ​​the distributed step area 115, and the third step area 115c may be a lateral (e.g., in the Y direction) terminal step area of ​​the distributed step area 115. The first step area 115a, the second step area 115b, and the third step area 115c may be collectively referred to herein as "step area 115".

[0038] although Figure 1A Only three stepped areas 115 (first stepped area 115a, second stepped area 115b, and third stepped area 115c) are described, but this disclosure is not limited thereto. In other embodiments, the microelectronic device structure 100 may include more than three (3) stepped areas (e.g., more than four (4), more than eight (8), more than twelve (12)), such as sixteen (16) stepped areas. For example, the second stepped area 115b (i.e., the stepped area located between the lateral terminal stepped areas) may include more than one (1) stepped area (e.g., more than four (4), more than eight (8), more than twelve (12) stepped areas).

[0039] Each of the first step region 115a, the second step region 115b, and the third step region 115c may include at least one step structure 140, said step structure comprising a step 142 (e.g., a contact area) defined by a lateral edge (e.g., an end) of layer 108. As will be described herein, the step structure 140 of the first step region 115a and the third step region 115c may include a selected gate structure (SGS), such as a selected gate drain (SGD) structure, and may be referred to herein as a selected gate drain step structure.

[0040] Laterally adjacent stepped areas 115 (e.g., in the Y direction) can be connected by relatively vertically rising areas (e.g., rising area 340) that do not contain steps 142. Figure 3 The first step zone 115a can be separated from each other by a first vertical rise zone (e.g., rise zone 340) that does not contain step 142. Figure 3 It is separated from the second step area 115b; and the second step area 115b can be separated from the third step area 115c through a second relatively vertically rising area that does not contain step 142.

[0041] The total number of steps 142 contained in the distributed staircase area 115 may be substantially the same as (e.g., equal to) the number of layers 108 in the stacked structure 102, or may be different from (e.g., less than, greater than) the number of layers 108 in the stacked structure 102. Figure 1A As shown, in some embodiments, the steps 142 of each of the stepped structures 140 are arranged in sequence such that steps 142 that are directly horizontally adjacent to each other in the Y direction correspond to layers 108 of stacked structures 102 that are directly vertically adjacent to each other (e.g., in the Z direction). In additional embodiments, the steps 142 of at least one of the stepped structures 140 are arranged in a disordered manner such that at least some steps 142 of the stepped structures 140 that are directly horizontally adjacent to each other in the Y direction correspond to layers 108 of stacked structures 102 that are not directly vertically adjacent to each other (e.g., in the Z direction).

[0042] Dielectric material 116 may be vertically (e.g., in the Z direction) over the uppermost vertical layer 108 of insulating structure 104 and additional insulating structure 106. Dielectric material 116 may include one or more of the materials described above with reference to insulating structure 104. In some embodiments, dielectric material 116 includes silicon dioxide.

[0043] Continue to refer to Figure 1A and Figure 1B The post 120 may extend vertically (e.g., in the Z direction) through the stacked structure 102. In some embodiments, the post 120 extends at least partially into the source layer 110 (e.g., at least partially into the first source material 112).

[0044] Column 120 may have a horizontal dimension (e.g., diameter) D1 in the range of about 60 nanometers (nm) to about 120 nm, for example, about 60 nm to about 80 nm, about 80 nm to about 100 nm, or about 100 nm to about 120 nm. Figure 1B In some embodiments, the horizontal dimension D1 is about 80 nm to about 100 nm. However, this disclosure is not limited thereto, and the horizontal dimension D1 may differ from those described.

[0045] refer to Figure 1B The pillars 120 that are laterally adjacent to each other in the Y direction can be offset from each other in the X direction. Therefore, the pillars 120 can be arranged in a so-called woven pattern, which can facilitate the formation of the pillars 120 (and the resulting memory cells (e.g., memory cell 174)). Figure 1I )) of strings (e.g., string 172) Figure 1I The density of the columns increases. However, this disclosure is not limited thereto, and the columns 120 may be arranged in other patterns (e.g., lines in which the columns 120 of each line are aligned with the columns 120 of each of the other lines). In some embodiments, each column 120 may be surrounded by six (6) other columns 120 and may be arranged in a hexagonal pattern.

[0046] For clarity and ease of understanding of the description, Figure 1A The distance between the columns 120 is enlarged. It should be understood that the lateral (e.g., in the Y direction) distance between the columns 120 may be less than... Figure 1A The distances described in the text, for example Figure 1B The relative distances described in the text.

[0047] The material of pillar 120 can be used to form memory cells (e.g., vertically extending strings of NAND memory cells). Reference Figure 1A Each pillar 120 may individually include a charge-blocking material (also referred to as a "dielectric barrier material") 122 that is horizontally adjacent to an insulating structure 104 and an additional insulating structure 106 of one of the layers 108 of the stacked structure 102; a memory material 124 that is horizontally adjacent to the charge-blocking material 122; a tunneling dielectric material (also referred to as a "tunneling dielectric material") 126 that is horizontally adjacent to the memory material 124; a channel material 128 that is horizontally adjacent to the tunneling dielectric material 126; and an insulating material 130 that is horizontally adjacent to the channel material 128 and located in the central portion of the pillar 120. The channel material 128 can be horizontally inserted between the insulating material 130 and the tunnel dielectric material 126; the tunnel dielectric material 126 can be horizontally inserted between the channel material 128 and the memory material 124; the memory material 124 can be horizontally inserted between the tunnel dielectric material 126 and the charge blocking material 122; and the charge blocking material 122 can be horizontally inserted between the memory material 124 and the layers of the insulating structure 104 and the additional insulating structure 106. The charge blocking material 122, the memory material 124, and the tunnel dielectric material 126 can be collectively referred to herein as "memory cell materials".

[0048] refer to Figure 1B For clarity and ease of understanding of the description, Figure 1BIn the diagram, pillar 120 is described, while there is no charge-blocking material 122, memory material 124, tunnel dielectric material 126, channel material 128, and conductive material 132. However, it should be understood that... Figure 1B The circle containing column 120 in the middle is explained. Figure 1A The description in Figure 1B Each of the charge blocking material 122, memory material 124, tunnel dielectric material 126, channel material 128, and conductive material 132 within the cross-section.

[0049] Return to reference Figure 1A In some embodiments, the pillar 120 includes a barrier material horizontally intervening between the charge-blocking material 122 and the layers of the insulating structure 104 and the additional insulating structure 106. In some such embodiments, the barrier material may be formed of one or more of the following and includes one or more of the following: metal oxides (e.g., one or more of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, gadolinium oxide, niobium oxide, and titanium oxide), dielectric silicides (e.g., aluminum silicide, hafnium silicate, zirconium silicate, lanthanum silicide, yttrium silicide, and tantalum silicide), and dielectric nitrides (e.g., aluminum nitride, hafnium nitride, lanthanum nitride, yttrium nitride, and tantalum nitride). In some embodiments, the barrier material includes aluminum oxide.

[0050] The charge blocking material 122 may be formed of a dielectric material and may contain one or more of a dielectric material, such as an oxide (e.g., silicon dioxide), a nitride (silicon nitride), and an oxide oxynitride (silicon oxynitride), or another material. In some embodiments, the charge blocking material 122 comprises silicon oxynitride.

[0051] Memory material 124 may include charge-trapping materials or conductive materials. Memory material 124 may be formed from and include one or more of the following: silicon nitride, silicon oxynitride, polycrystalline silicon (doped polycrystalline silicon), conductive materials (tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and alloys thereof, or metal silicides, such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof), semiconducting materials, polycrystalline or amorphous semiconductor materials, materials containing at least one elemental semiconductor element and / or at least one compound semiconductor material, conductive nanoparticles (e.g., ruthenium nanoparticles), and metal dots. In some embodiments, memory material 124 includes silicon nitride.

[0052] The tunnel dielectric material 126 may be formed of and comprise a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions, for example, by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer. By way of non-limiting examples, the tunnel dielectric material 126 may be formed of and comprise one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In some embodiments, the tunnel dielectric material 126 comprises silicon dioxide. In other embodiments, the tunnel dielectric material 126 comprises nitrogen, such as oxynitride. In some such embodiments, the tunnel dielectric material 126 comprises silicon oxynitride.

[0053] In some embodiments, the tunnel dielectric 126, memory material 124, and charge blocking material 122 together may include a structure configured to trap charge, such as an oxide-nitride-oxide (ONO) structure. In some such embodiments, the tunnel dielectric 126 comprises silicon dioxide, the memory material 124 comprises silicon nitride, and the charge blocking material 122 comprises silicon dioxide. In other embodiments, the tunnel dielectric 126, memory material 124, and charge blocking material 122 together comprise an oxide-nitride-oxide-oxygen nitride structure. In some such embodiments, the tunnel dielectric 126 comprises silicon oxynitride, the memory material 124 comprises silicon nitride, and the charge blocking material 122 comprises silicon dioxide.

[0054] The channel material 128 may be formed from one or more of the following and includes one or more of the following: semiconductor materials (at least one elemental semiconductor material, such as polycrystalline silicon; at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, GaAs, InP, GaP, GaN, other semiconductor materials) and oxide semiconductor materials. In some embodiments, the channel material 128 comprises amorphous silicon or polycrystalline silicon. In some embodiments, the channel material 128 comprises a doped semiconductor material.

[0055] The insulating material 130 may be formed of and comprise an insulating material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), nitrogen oxides (e.g., silicon oxynitride), dielectric carbon nitride materials (e.g., silicon carbon nitride (SiCN)), dielectric carbon oxynitride materials (e.g., silicon carbon oxynitride (SiOCN)), or combinations thereof. In some embodiments, the insulating material 130 comprises silicon dioxide.

[0056] Continue to refer to Figure 1A The conductive contact structure 135 may be formed to be electrically connected to the channel material 128 of the post 120. For example, in some embodiments, a portion of the insulating material 130 within the post 120 may be selectively removed to form a recess in each of the posts 120. After the selective removal of the insulating material 130, a conductive material 132 may be formed within the recess of each post 120 and to be electrically connected to the channel material 128. The conductive material 132 may be formed of, for example, tungsten and may contain, for example, tungsten. In other embodiments, the conductive material 132 comprises polycrystalline silicon.

[0057] The conductive contact structure 135 may be electrically connected to, for example, a conductive line (e.g., a bit line) for providing access to memory cells (e.g., memory cells 174) formed by the pillars 120. Figure 1I Access to strings (e.g., string 172 (Figure IH)).

[0058] Additional dielectric material 134 may be vertically (e.g., in the Z direction) overlying the stacked structure 102 and the pillars 120. The additional dielectric material 134 may be formed of and contain an insulating material. In some embodiments, the additional dielectric material 134 comprises the same material composition as the insulating structure 104. In some embodiments, the additional dielectric material 134 comprises silicon dioxide.

[0059] Etch-stop material 136 may be vertically (e.g., in the Z direction) overlying additional dielectric material 134. Etch-stop material 136 may exhibit etch selectivity relative to additional dielectric material 134 and dielectric material 138 vertically overlying etch-stop material 136 and step region 115. Dielectric material 138 may be formed of and comprise one or more of the materials described above with reference to dielectric material 118. In some embodiments, dielectric material 138 comprises silicon dioxide.

[0060] The etch stop material 136 may be formed from and include the following: dielectric carbon nitride material (e.g., silicon carbon nitride (SiCN)) and dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiOCN)). In some embodiments, the etch stop material 136 comprises carbon-doped silicon nitride.

[0061] The thickness of the etch-stop material 136 (e.g., in the Z direction) can be approximately 150 angstroms. To date For example, about To date or about To date Within the range. In some embodiments, the thickness of the etch-stop material 136 is approximately

[0062] refer to Figures 1C to 1E The first support column structure 152 and the second support column structure 154 may be formed within a distributed stepped area 115, such as within a first stepped area 115a, a second stepped area 115b, and a third stepped area 115c. For example, the first support column structure 152 may be formed as a stacked structure 102 extending vertically (e.g., in the Z direction) through the first stepped area 115a and the third stepped area 115c, and the second support column structure 154 may be formed as a stacked structure 102 extending vertically through the second stepped area 115b. The first support column structure 152 and the second support column structure 154 may be collectively referred to herein as "support column structures". Figure 1D for Figure 1C A simplified top view of the first step region 115a of the microelectronic device structure 100, and Figure 1E for Figure 1C A simplified top view of the second step region 115b of the microelectronic device structure 100.

[0063] The first support column structure 152 may have a larger lateral dimension (e.g., diameter) D3 than the second support column structure 154. Figure 1E The lateral dimension (e.g., diameter) D2 ( Figure 1D In some embodiments, the first support column structure 152 exhibits a larger cross-sectional area than the second support column structure 154.

[0064] The lateral dimension D2 of the first support column structure 152 can be in the range of about 200 nm to about 600 nm, for example, about 200 nm to about 300 nm, about 300 nm to about 400 nm, about 400 nm to about 500 nm, or about 500 nm to about 600 nm. In some embodiments, the lateral dimension D2 is greater than about 200 nm, for example, greater than about 400 nm, or greater than about 600 nm.

[0065] The lateral dimension D3 of the second support column structure 154 can be in the range of about 150 nm to about 400 nm, for example, about 150 nm to about 200 nm, about 200 nm to about 300 nm or about 300 nm to about 400 nm.

[0066] The first support pillar structure 152 and the second support pillar structure 154 may each individually include a first material 156 extending vertically (e.g., in the Z direction) through the stacked structure 102 and reaching the source layer 110, and a lining material 158 located on the sidewall of the first material 156. The lining material 158 may substantially surround (e.g., substantially horizontally and vertically cover) the sidewall of the first material 156.

[0067] The first material 156 may be formed of and contain at least one conductive material, such as one or more of the following: metals (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni, and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe). In some embodiments, the first material 156 of each of the support pillar structures 152, 154 has substantially the same material composition.

[0068] In other embodiments, the first material 156 is formed of and comprises an insulating material. In some such embodiments, the first material 156 may be formed of and comprises at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y), and at least one dielectric carbon oxynitride material (e.g., SiO2). x C z N y It may be one or more of amorphous carbon. In some embodiments, the first material 156 includes SiO2. In some embodiments, such as when the first material 156 includes an insulating material, the support pillar structures 152, 154 may not include the lining material 158 on the sidewalls of the first material 156, and the support pillar structures 152, 154 may include only the first material 156 (e.g., an insulating material).

[0069] The lining material 158 can be horizontally inserted between each of the first materials 156 of the support pillar structures 152, 154 and the layer 108 of the stacked structure 102 (including its insulating structure 104 and additional insulating structure 106). The lining material 158 may be formed of one or more of the following and includes one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x ,TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO2). x C z N y ( ) and amorphous carbon. In some embodiments, the lining material 158 comprises SiO2. In some embodiments, the lining material 158 has a different material composition than the dielectric material 138. In other embodiments, the lining material 158 has the same material composition as the dielectric material 138. In some embodiments, the lining material 158 comprises a material composition that is substantially not removed in response to exposure to etching chemicals formulated and configured to remove silicon nitride.

[0070] The support pillar structures 152 and 154 can each individually exhibit the desired geometric configuration (e.g., size and shape) and spacing. The geometric configuration and spacing of the support pillar structures 152 and 154 can be based at least in part on the configuration and position of other components of the microelectronic device structure 100 (e.g., the step 142 of the stepped structure 140, the first conductive contact structure 150 to be formed to contact the step 142 of the stepped structure 140 with the first stepped region 115a and the third stepped region 115c). Figure 1K ), and the second conductive contact structure 175 to be formed to contact the step 142 of the stepped structure 140 of the second stepped region 115b. Figure 1N The support pillar structures 152 and 154 are selected based on the source layer 110. For example, each of the support pillar structures 152 and 154 may individually have a certain geometric configuration and spacing that allows the support pillar structures 152 and 154 to extend vertically (e.g., in the Z direction) through the stack structure 102 and to make structural physical contact with (e.g., land on) the source layer 110 to facilitate the predetermined functions of the support pillar structures 152 and 154 (e.g., electrical interconnection functions, support functions). In other embodiments, the support pillar structures 152 and 154 do not include electrical interconnection functions and primarily (e.g., only) provide support functions.

[0071] Each of the first support column structures 152 may exhibit substantially the same geometric configuration (e.g., same size and shape) and horizontal spacing (e.g., in the X direction) as each of the other first support column structures 152, or at least some of the first support column structures 152 may exhibit different geometric configurations (e.g., one or more different sizes, different shapes) and / or different horizontal spacings than at least some of the other first support column structures 152. In some embodiments, the first support column structures 152 are at least partially uniformly spaced in the X direction and in the Y direction. In some embodiments, the first support column structures 152 are arranged as rows extending in the X direction and columns extending in the Y direction. In other embodiments, the first support column structures 152 are at least partially non-uniformly spaced in the X direction.

[0072] In some embodiments, the first support column structure 152 exhibits an elliptical cross-sectional shape. For example, in some embodiments, the first support column structure 152 exhibits an elliptical shape and extends in a lateral direction (e.g., the Y direction).

[0073] Each of the second support column structures 154 may exhibit substantially the same geometric configuration (e.g., same size and shape) and horizontal spacing (e.g., in the X direction) as each of the other second support column structures 154, or at least some of the second support column structures 154 may exhibit different geometric configurations (e.g., one or more different sizes, different shapes) and / or different horizontal spacings than at least some of the other second support column structures 154. In some embodiments, the second support column structures 154 are at least partially uniformly spaced in the X direction and in the Y direction. In some embodiments, the second support column structures 154 are arranged as rows extending in the X direction and columns extending in the Y direction. In other embodiments, the second support column structures 154 are at least partially non-uniformly spaced in the X direction.

[0074] In some embodiments, the second support column structure 154 exhibits a substantially circular transverse cross-sectional shape. In some embodiments, the second support column structure 154 exhibits a different transverse cross-sectional shape than the first support column structure 152. In some embodiments, the first support column structure 152 exhibits a transverse dimension (e.g., length, diameter) larger than the dimensions (e.g., length, diameter) of the second support column structure 154.

[0075] The support pillar structures 152 and 154 may serve as support structures during and / or after the formation of one or more components of the microelectronic device structure 100. For example, the support pillar structures 152 and 154 may serve as conductive structures formed during the replacement of the additional insulating structure 106 with a conductive structure (e.g., conductive structure 162). Figure 1F The supporting structures, as described herein, include support columns 152 and 154 that can prevent (e.g., prevent) layer collapse during the selective removal of additional insulation structure 106.

[0076] Common Reference Figures 1F to 1H After the first support column structure 152 and the second support column structure 154 are formed, a groove structure 160 can be formed through the stacked structure 102. Figure 1G , Figure 1H The trench structure 160 may be formed within a trench (e.g., an opening, an aperture) formed through the stacked structure 102 to facilitate the operation of the conductive structure 162 by so-called “replacement gate” or “gate persistence” processing. Figure 1F Replace additional insulation structure 106 ( Figure 1C The slot structure 160 can be horizontally inserted into the block structure 164 formed by separating the stacked structure 102 from the slots used for gate replacement processing. Figure 1G , Figure 1H Between ), in other words, the slot structure 160 can separate the microelectronic device structure 100 into a block structure 164. Figure 1G For crossing Figure 1F A simplified top view of a portion of the first stepped region 115a intercepted by section line GG, and Figure 1H For crossing Figure 1F A simplified top view of a portion of the second step zone 115b, cut by the section line HH.

[0077] In some embodiments, each structure 164 includes four (4) columns of first support column structures 152 or second support column structures 154 located between horizontally adjacent slot structures 160. However, this disclosure is not limited thereto, and in other embodiments, each structure 164 may include fewer (e.g., three, two, one) columns of first support column structures 152 and second support column structures 154; or each structure 164 may include more (e.g., five, six, seven, eight) columns of first support column structures 152 and second support column structures 154.

[0078] A trench (also referred to herein as a “replacement gate trench”) can be formed through the stacked structure 102 at a location corresponding to trench structure 160 to extend through dielectric material 138, additional dielectric material 134, etch stop material 136, dielectric material 116, and insulating structure 104 and additional insulating structure 106. Figure 1C Layer 108. In some embodiments, the trench may expose source layer 110, such as first source material 112.

[0079] Additional insulation structure 106 ( Figure 1C The insulating structure 104 can be selectively removed (e.g., excavated) via a slot. The space between vertically adjacent (e.g., in the Z direction) insulating structures 104 can be filled with a conductive material to form a conductive structure 162 and a stacked structure 166 comprising a layer 168 containing the insulating structure 104 and the conductive structure 162. The conductive structure 162 can be located at a position corresponding to the location of the additional insulating structure 106 removed via the slot.

[0080] After the conductive structure 162 is formed, the trench may be filled with one or more materials to form the trench structure 160. In some embodiments, the trench structure 160 includes an insulating material 170. The insulating material 170 may include one or more of the materials described above with reference to the insulating structure 104. In some embodiments, the insulating material 170 includes silicon dioxide. In other embodiments, the trench structure 160 includes, for example, a lining material on its sidewalls and a conductive material horizontally adjacent to the lining material. In some such embodiments, the lining material may include an insulating material, such as silicon dioxide; and the conductive material may include polysilicon or tungsten and may be electrically connected to the source layer 110 (e.g., through the first source material 112).

[0081] although Figure 1G and Figure 1HThe description includes only two slot structures 160 and only three block structures 164, but this disclosure is not limited thereto. The microelectronic device structure 100 may include multiple (e.g., four, five, six, or eight) block structures 164, each separated from laterally adjacent (e.g., in the Y direction) block structures 164 by slot structures 160. In other words, slot structures 160 can divide the microelectronic device structure 100 into any desired number of block structures 164.

[0082] The conductive structure 162 may be formed of and contain at least one conductive material, such as at least one metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), or at least one alloy (e.g., Co-based alloys, Fe-based alloys, etc.). The conductive structure 162 may be composed of or contain at least one conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)), at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), or combinations thereof. In some embodiments, the conductive structure 162 is formed of and contains tungsten.

[0083] Each of the conductive structures 162 may individually comprise at least one conductive material that is substantially uniformly distributed or substantially non-uniformly distributed. In some embodiments, each of the conductive structures 162 of each of the layers 168 of the stacked structure 166 exhibits a substantially uniformly distributed conductive material. In additional embodiments, at least one of the conductive structures 162 of at least one of the layers 168 of the stacked structure 166 exhibits a substantially non-uniformly distributed at least one conductive material. The conductive structure 162 may be formed, for example, by and comprise a stack of at least two different conductive materials. The conductive structures 162 of each of the layers 168 of the stacked structure 166 may each be substantially planar and may each exhibit a desired thickness.

[0084] In some embodiments, the conductive structure 162 may include a conductive liner material surrounding the conductive structure 162, for example, between the conductive structure 162 and the insulating structure 104. The conductive liner material may include, for example, a seed material, and the conductive structure 162 may be formed from said seed material. The conductive liner material may be formed from and include, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, the conductive liner material includes titanium nitride.

[0085] At least one lower conductive structure 162 of the stacked structure 166 may be used as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the microelectronic device structure 100. In some embodiments, a single (e.g., only one) conductive structure 162 of the vertically bottommost layer 168 of the stacked structure 166 may be used as a lower select gate (e.g., SGS) of the microelectronic device structure 100. Additionally, the upper conductive structure 162 of the stacked structure 166 may be used as an upper select gate (e.g., drain-side select gate (SGD)) of the microelectronic device structure 100. In some embodiments, horizontally adjacent conductive structures 162 of the vertically topmost layer 168 of the stacked structure 166 (e.g., separated from each other by additional trench structures) may be used as upper select gates (e.g., SGDs) of the microelectronic device structure 100. In some embodiments, more than one (e.g., two, four, five, or six) conductive structures 162 may be used as upper select gates (e.g., SGDs) of the microelectronic device structure.

[0086] Continue to refer to Figure 1F The formation of conductive structure 162 can form strings 172 of memory cells 174, each memory cell 174 being located at the intersection of conductive structure 162 with memory cell material (e.g., charge blocking material 122, memory material 124, tunnel dielectric material 126) and channel material 128. Each structure 164 may contain multiple strings 172 of memory cells 174. As will be described herein, each structure 164 may contain stepped structures (e.g., stepped structures 140, stepped structures 220) that are laterally offset (e.g., in the X direction) from the strings 172 of memory cells 174. Figure 2 The string 172 of memory cell 174 may be located within the horizontal boundary of conductive structure 162 of layer 168. The string 172 may be located within the horizontal boundary of array region 105.

[0087] Although the microelectronic device structure 100 has been described and illustrated as including a memory cell 174 with a specific configuration, this disclosure is not limited thereto. In some embodiments, the memory cell 174 may include a so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cell. In additional embodiments, the memory cell 174 includes a so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cell or a so-called "BETANOS" (band / barrier engineered TANOS) memory cell, each of which is a subset of MONOS memory cells. In other embodiments, the memory cell 174 includes a so-called "floating gate" memory cell, which includes a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally positioned between the central structure of string 172 and the conductive structure 162.

[0088] Common Reference Figure 1I and Figure 1J After the groove structure 160 is formed, the block structure 164 can be connected via the additional groove structure 180. Figure 1J The array region 105, the first step region 115a, and the third step region 115c are divided into sub-block structures 178. Figure 1J ). Figure 1J For crossing Figure 1I The cross-section line JJ intercepted Figure 1I A simplified partial top view of a portion of the first stepped region 115a of the microelectronic device structure 100. Each of the sub-block structures 178 may be defined within the lateral boundaries of the individual block structure 164. In some embodiments, an additional slot structure 180 defines four (4) sub-block structures 178 located within the lateral boundaries of the individual block structures 164. It should be understood that in some embodiments, the third stepped region 115c may be divided into sub-block structures 178, as described with reference to the first stepped region 115a.

[0089] The additional slot structure 180 may extend vertically (e.g., in the Z direction) through the stacked structure 166. Figure 1I A portion of the slot structure 160 (e.g., the vertical upper portion) is less than the distance by which the slot structure 160 extends vertically through the stacked structure 166. The additional slot structure 180 may extend parallel in the lateral direction (e.g., in the Y direction) and may also extend parallel in the lateral direction to the slot structure 160. As used herein, "parallel" means substantially parallel.

[0090] The additional trench structure 180 may include an insulating material 182, such as one or more of the materials described above for the insulating material 170 of the reference trench structure 160. In some embodiments, the insulating material 182 comprises the same material composition as the insulating material 170. In some embodiments, the insulating material 182 comprises silicon dioxide.

[0091] In some embodiments, the additional slot structure 180 is located within the first stepped region 115a and the third stepped region 115c but not within the second stepped region 115b. In some such embodiments, the additional slot structures 180 of the laterally adjacent first support column structures 152 extend in the lateral direction (e.g., the Y direction) in which the additional slot structures 180 extend. The first conductive contact structure 150 may be located between the laterally adjacent additional slot structures 180.

[0092] Continue to refer to Figure 1I and Figure 1J An opening 144 is formed by passing through the dielectric material 138 within the array region 105 and through the dielectric material 138 within the first step region 115a and the third step region 115c. The opening 144 in the array region 105 may expose additional dielectric material 134 in the first step region 115a and a portion of the opening 144, and the third step region 115c may expose portions of some of the conductive structures 162. In some embodiments, the opening 144 within the array region 105 terminates on or within the etch stop material 136.

[0093] In some embodiments, the etch-stop material 136 within the array region 105 may act as an etch-stop layer during the formation of the opening 144 within the array region 105. For example, the dielectric material 138 may exhibit etch selectivity relative to the etch-stop material 136 in the range of about 20:1 to about 60:1, such as about 20:1 to about 40:1 or about 40:1 to about 60:1. In other words, the dielectric material 138 may be removed at a rate of about 20 to about 60 times faster than the etch-stop material 136. The etch-stop material 136 within the array region 105 may facilitate the formation of the opening 144 within the first stepped region 115a and the third stepped region 115c to have a greater vertical (e.g., in the Z direction) height than the opening 144 within the array region 105 without removing a portion of the conductive contact structure 135.

[0094] The upper vertical (e.g., in the Z direction) portion of the opening 144 may have a diameter D4 larger than the diameter D5 of the lower portion of the opening 144. The diameter D4 may be in the range of about 50 nanometers (nm) to about 120 nm, for example, about 50 nm to about 60 nm, about 60 nm to about 80 nm, about 80 nm to about 100 nm, or about 100 nm to about 120 nm. In some embodiments, the diameter D4 is about 90 nm to about 100 nm. The diameter D4 may also be in the range of about 40 nm to about 80 nm, for example, about 40 nm to about 50 nm, about 50 nm to about 60 nm, about 60 nm to about 70 nm, or about 70 nm to about 80 nm. In some embodiments, the diameter D5 is in the range of about 50 nm to about 60 nm. However, this disclosure is not limited thereto, and the diameters D4 and D5 may differ from those described.

[0095] In some embodiments, the openings 144 in the first stepped region 115a and the third stepped region 115c are substantially the same size (e.g., diameters D4, D5) as the openings 144 in the array region 105. In some embodiments, the diameter D4 of the openings 144 in the first stepped region 115a and the third stepped region 115c is substantially the same as the diameter D4 of the openings 144 in the array region 105.

[0096] Common Reference Figure 1K to Figure 1M The etch stop material 136 within the array region 105 is formed by the opening 144 ( Figure 1I The exposed portion of the group of materials can be removed (e.g., through) by opening 144, and the portion vertically lying on the additional dielectric material 134 can be removed by opening 144 to expose the portion of the conductive material 132 of the conductive contact structure 135. Figure 1L For crossing Figure 1K The section line LL intercepts Figure 1K A simplified top view of the first step zone 115a, and Figure 1M For crossing Figure 1K A simplified top view of the array region 105 taken by the cross-sectional line MM. A conductive contact 148 may be formed in the opening 144 in the array region 105, and a first conductive contact structure 150 may be formed in the opening 144 of the first stepped region 115a and the third stepped region 115c.

[0097] Conductive lining material 145 may be formed in opening 144 ( Figure 1I , Figure 1J The conductive material 146 can be formed on top of the conductive liner material 145 to form the conductive contact 148 in the array region 105 and the first conductive contact structure 150 in the first step region 115a and the third step region 115c.

[0098] The conductive material 146 of the conductive contact 148 and the first conductive contact structure 150 may contain at least one conductive material, such as one or more of the following: metals (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe). Each of the conductive contact 148 and the first conductive contact structure 150 may have substantially the same material composition, or at least one of the conductive contact 148 and the first conductive contact structure 150 may have a different material composition than at least one of the other two. In some embodiments, the conductive material 146 comprises tungsten.

[0099] The conductive liner material 145 of the conductive contact 148 and the first conductive contact structure 150 may include one or more of a conductive material, such as a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), and another material. In some embodiments, the conductive liner material 145 includes titanium nitride. In some embodiments, the conductive liner material 145 includes elemental titanium and titanium nitride. By way of a non-limiting example, titanium may define the outer portion of the conductive liner material 145 (e.g., the portion of the conductive liner material 145 in contact with the dielectric material 138), and titanium nitride may be overlaid on the titanium and located between the titanium and the conductive material 146.

[0100] although Figure 1L This disclosure describes some of the first conductive contact structures 150 that are laterally offset (e.g., in the X direction) from the center of the first support column structure 152 that is laterally adjacent (e.g., in the Y direction) to the first conductive contact structure 160, but is not limited thereto. In other embodiments, the first conductive contact structure 150 may be laterally aligned with the first support column structure 152.

[0101] Common Reference Figure 1N and Figure 10The second conductive contact structure 175 may be formed as a conductive structure 162 that extends vertically through the dielectric material 138 and individually contacts the conductive structure 166 at the step 142 of the stepped structure 140 within the second stepped region 115b. The second conductive contact structure 175 may include a dielectric liner material 176 in contact with the dielectric material 138, a conductive liner material 177 in contact with the dielectric liner material 176, and a conductive material 179 in contact with the conductive liner material 177. The dielectric liner material 176 may include dielectric material that can be formed in a high aspect ratio (HAR) opening. By way of non-limiting examples, the dielectric liner material 176 may comprise silicon dioxide or metal oxides (e.g., one or more of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, gadolinium oxide, niobium oxide, titanium oxide, and magnesium oxide), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, and at least one dielectric nitride material (e.g., silicon nitride (SiN)). y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y )).

[0102] The conductive liner material 177 may include the first conductive contact structure 150 as described above. Figure 1K ) conductive lining material 145 ( Figure 1K The conductive liner material 177 may be one or more of the materials described herein. In some embodiments, the conductive liner material 177 comprises substantially the same material composition as the conductive liner material 145 of the first conductive contact structure 150. In some embodiments, the conductive liner material 177 comprises titanium and titanium nitride.

[0103] The conductive material 179 may include the first conductive contact structure 150 as described above. Figure 1K ) conductive material 146 ( Figure 1K The materials described herein may be one or more. In some embodiments, the conductive material 179 of the second conductive contact structure 175 comprises substantially the same material composition as the conductive material 146 of the first conductive contact structure 150. In some embodiments, the conductive material 179 comprises tungsten.

[0104] The lateral dimension (e.g., diameter) D6 of the upper vertical (e.g., in the Z direction) portion of each of the second conductive contact structures 175 may be larger than the lateral dimension (e.g., diameter) D7 of the lower vertical portion of each of the second conductive contact structures 175. In some embodiments, dimension D6 is in the range of about 150 nm to about 300 nm, for example, about 150 nm to about 200 nm, about 200 nm to about 250 nm, or about 250 nm to about 300 nm. Dimension D7 may be in the range of about 100 nm to about 200 nm, for example, about 100 nm to about 150 nm, or about 150 nm to about 200 nm.

[0105] Common Reference Figure 1I , Figure 1L , Figure 1N and Figure 10 The lateral dimensions D6 and D7 of the second conductive contact structure 175 within the second stepped region 115b may be greater than the corresponding lateral dimensions D4 and D5 of the first conductive contact structure 150 within the first stepped region 115a and the third stepped region 115c. By way of non-limiting examples, in some embodiments, the lateral dimensions D4 and D5 of the first conductive contact structure 150 may be less than half the lateral dimensions D6 and D7 of the second conductive contact structure 175. In some such embodiments, each of the second conductive contact structures 175 may individually have a lateral diameter greater than twice the lateral diameter of each individual first conductive contact structure 150.

[0106] The relatively small lateral dimensions D4 and D5 of the first conductive contact structure 150 can promote the lateral dimension D2 of the first support column structure 152 of the first stepped region 115a. Figure 1L The lateral dimension D3 of the second support column structure 154 relative to the second step zone 115b Figure 10 The relatively large lateral dimension D2 of the first support pillar structure 152 in the first step region 115a and the third step region 115c facilitates improved support for the insulating structure 104 during the "replacement gate" processing operation described above, to replace the additional insulating structure 106 with the conductive structure 162. Figure 1C In other words, when the additional insulating structure 106 is removed, the larger lateral dimension D2 of the first support pillar structure 152 can reduce the layer collapse of the layer 108 containing the insulating structure 104 during the "replace gate" processing operation.

[0107] Combination Reference Figure 1L and Figure 10 The first step zone 115a (and the third step zone 115c) can each be individually located at each step 142 ( Figure 1NThe first step 115a contains four (4) first conductive contact structures 150 for each second conductive contact structure 175 on each corresponding step 142 in the second step 115b. In other words, in some embodiments, the second conductive contact structure 175, the first step 115a may contain four (4) first conductive contact structures 150, and the third step 115c may contain four (4) first conductive contact structures 150.

[0108] Forming the first conductive contact structure 150 simultaneously with forming the conductive contact 148 electrically connected to the channel material 128 can help to form the first conductive contact structure 150 with a smaller lateral dimension (e.g., diameter) than the corresponding dimension of the second conductive contact structure 175. The smaller lateral dimension of the first conductive contact structure 150 can help increase the tolerance between the first conductive contact structure 150 and the first support post structure 152 (e.g., D8). Figure 1L In some embodiments, the first conductive contact structure 150 exhibits a relatively smaller lateral cross-sectional area than the second conductive contact structure 175. This increased tolerance can help increase the area (e.g., lateral cross-sectional area) used to form the first support pillar structure 152. Therefore, the first support pillar structure 152 can be formed with a larger lateral dimension (e.g., diameter, length) compared to support pillar structures in conventional microelectronic device structures without being electrically short-circuited to the first conductive contact structure 150. In some embodiments, the first support pillar structure 152 exhibits a larger lateral cross-sectional area than the second support pillar structure 154. The increased lateral dimension of the first conductive contact structure 150 helps reduce the amount of collapse of the first insulating structure 104 during the replacement gate processing operation described above.

[0109] In some embodiments, the step 142 of the first stepped region 115a including the first conductive contact structure 150 is vertically (e.g., in the Z direction) positioned higher than the step 142 of the second stepped region 115b. Forming the first conductive contact structure 150 simultaneously with the formation of the conductive contact 148, rather than during the formation of the second conductive contact structure 175, can help to form the first conductive contact structure 150 with smaller lateral dimensions D4, D5 than the second conductive contact structure 175. By comparison, forming the first conductive contact structure 150 simultaneously with the second conductive contact structure 175 can result in the formation of the opening 144 (…) of the first conductive contact structure 150. Figure 1I The reduction in polymer formation in the opening 144 results in a so-called "penetration phenomenon," where the opening 144 removes at least a portion of the uppermost vertical (e.g., in the Z direction) step 142.

[0110] Figure 2This illustration shows a partial cross-sectional perspective view of a portion of a microelectronic device 201 (e.g., a memory device, such as a dual-stack 3D NAND flash memory device) that includes a microelectronic device structure 200. The microelectronic device structure 200 may be substantially similar to that in the previous references. Figure 1N and Figure 10 The microelectronic device structure 100 following the described processing stage. (Example) Figure 2 As shown, the microelectronic device structure 200 may include features defining access lines 206 for connecting to a conductive layer 205 (e.g., a conductive layer, a conductive plate, such as conductive structure 162). Figure 1N The stepped structure 220 of the contact area (e.g., a stepped structure 140 including a first stepped area 115a, a second stepped area 115b, and a third stepped area 115c) Figure 1N The microelectronic device structure 200 may include memory cells 203 (e.g., memory cell 174) coupled in series with each other. Figure 1N The vertical string 207 (e.g., string 172) Figure 1N Vertical string 207 may extend vertically (e.g., in the Z direction) and orthogonally to conductive lines and layer 205, such as data line 202, source layer 204 (e.g., source structure 110). Figure 1N The system includes a conductive layer 205, access lines 206, a first select gate 208 (e.g., upper select gate, drain select gate (SGD)), select lines 209, and a second select gate 210 (e.g., lower select gate, source select gate (SGS)). The select gate 208 can be horizontally divided (e.g., in the Y direction) into multiple blocks 232 (e.g., block structure 164). Figure 1L , Figure 10 The plurality of blocks are connected by a groove structure 230 (e.g., a filled groove, such as a groove structure 160 filled with one or more insulating materials). Figure 1L , Figure 10 They are horizontally separated from each other.

[0111] Vertical conductive contact 211 (e.g., first conductive contact structure 150) Figure 1K , Figure 1L ), second conductive contact structure 175 ( Figure 1N , Figure 10Components can be electrically coupled to each other as shown. For example, select line 209 can be electrically coupled to first select gate 208, and access line 206 can be electrically coupled to conductive layer 205. Microelectronic device 201 may also include a control unit 212 located below the memory array, which may include control logic configured to control various operations of other features of microelectronic device 201 (e.g., string 207 of memory cells 203). By way of a non-limiting example, control unit 212 may include one or more (e.g., each) of the following: a charge pump (e.g., V... CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuit systems (e.g., ring oscillators), V dd The control unit 212 includes regulators, drivers (e.g., serial drivers), decoders (e.g., local stack decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh / wear-out equalization devices, and other chip / stack control circuitry. The control unit 212 may be electrically coupled to, for example, data line 202, source layer 204, access line 206, first select gate 208, and second select gate 210. In some embodiments, the control unit 212 includes a complementary metal-oxide-semiconductor (CMOS) circuitry. In such embodiments, the control unit 212 may be characterized by having an "array-under-CMOS" ("CuA") configuration.

[0112] The first selection gate 208 may extend horizontally in a first direction (e.g., the X direction) and may be coupled at a first end (e.g., the upper end) of the vertical string 207 to a corresponding first group of vertical strings 207 of the memory cell 203. The second selection gate 210 may be formed in a substantially planar configuration and may be coupled at a second opposite end (e.g., the lower end) of the vertical string 207 of the memory cell 203 to the vertical string 207.

[0113] Data lines 202 (e.g., digital lines, bit lines) may extend horizontally in a second direction (e.g., in the Y direction) at an angle (e.g., perpendicular) to a first direction in which the first select gate 208 extends. Data lines 202 may be coupled to a corresponding second group of vertical strings 207 at a first end (e.g., the upper end). The first group of vertical strings 207 coupled to the corresponding first select gate 208 may share a specific vertical string 207 with the second group of vertical strings 207 coupled to the corresponding data lines 202. Therefore, a specific vertical string 207 may be selected at the intersection of a specific first select gate 208 and a specific data line 202. Thus, the first select gate 208 can be used to select a memory cell 203 of a string 207 of memory cells 203.

[0114] Conductive layer 205 (e.g., word line board), conductive structure 162 (e.g., Figure 1N The conductive layers 205 can extend in a corresponding horizontal plane. The conductive layers 205 can be stacked vertically such that each conductive layer 205 is coupled to all vertical strings 207 of the memory cells 203, and the vertical strings 207 of the memory cells 203 extend vertically through the stack of conductive layers 205. The conductive layers 205 can be coupled to or can form the control gate of the memory cells 203, and the conductive layers 205 are coupled to the control gate. Each conductive layer 205 can be coupled to one memory cell 203 in a specific vertical string 207 of the memory cells 203.

[0115] The first select gate 208 and the second select gate 210 are operable to select a specific vertical string 207 of memory cells 203 between a specific data line 202 and the source layer 204. Thus, a specific memory cell 203 can be selected and electrically coupled to the data line 202 by operating (e.g., by selecting) the appropriate first select gate 208, second select gate 210, and conductive layer 205 coupled to the specific memory cell 203.

[0116] The stepped structure 220 can be configured to provide an electrical connection between the access line 206 and the conductive layer 205 via a vertical conductive contact 211. In other words, a specific level of layer 205 can be selected via an access line 206 electrically connected to a corresponding vertical conductive contact 211 electrically connected to the same specific layer 205.

[0117] Data cable 202 can be connected via conductive contact structure 234 (e.g., conductive contact 148). Figure 1N Electrically coupled to vertical string 207.

[0118] Figure 3 This is a simplified perspective view of a microelectronic device structure 300 according to an embodiment of the present disclosure. The microelectronic device structure 300 can be used, for example, as a prior reference. Figure 2The microelectronic device structure 200 of the described microelectronic device 201 or the previously referenced Figure 1N and Figure 10 The described microelectronic device structure 100. (e.g.) Figure 3 As shown, the microelectronic device structure 300 may include a stacked structure 305 of vertically alternating conductive and insulating structures (e.g., stacked structure 166). Figure 1N The microelectronic device structure 300 may include one or more stepped structures 310 (e.g., stepped structure 140). Figure 1N ), stepped structure 220 ( Figure 2 The steps 311 of the stepped structure 310 of the microelectronic device structure 300 can serve as different layers for the stacked structure 305 (e.g., conductive materials (e.g., conductive structure 162)). Figure 1H The conductive layer 205 of the )) Figure 2 The contact area of ​​the conductive structure (e.g., conductive layer 205) and the horizontal end of the insulating structure located between adjacent conductive structures.

[0119] The stepped structure 310 may include, for example, a first stadium structure 301, a second stadium structure 302, a third stadium structure 303, and a fourth stadium structure 304. Each of the first stadium structure 301, the second stadium structure 302, the third stadium structure 303, and the fourth stadium structure 304 may include steps 311 at different heights (e.g., vertical positions) relative to the steps 311 of the other three stadium structures. The first stadium structure 301 may include a first stepped structure 301a and an additional first stepped structure 301b; the second stadium structure 302 may include a second stepped structure 302a and an additional second stepped structure 302b; the third stadium structure 303 may include a third stepped structure 303a and an additional third stepped structure 303b; and the fourth stadium structure 304 may include a fourth stepped structure 304a and an additional fourth stepped structure 304b. The first stepped structure 301a, the second stepped structure 302a, the third stepped structure 303a, and the fourth stepped structure 304a may include steps 311 at the same height as the corresponding additional first stepped structure 301b, additional second stepped structure 302b, additional third stepped structure 303b, and additional fourth stepped structure 304b. Each of the first stepped structure 301a, the second stepped structure 302a, the third stepped structure 303a, and the fourth stepped structure 304a may individually exhibit a generally negative slope; and each of the additional first stepped structure 301b, the additional second stepped structure 302b, the additional third stepped structure 303b, and the additional fourth stepped structure 304b may individually exhibit a generally positive slope.

[0120] like Figure 3 As shown, valley 325 may be located between the first stepped structure 301a and the additional first stepped structure 301b; between the second stepped structure 302a and the additional second stepped structure 302b; between the third stepped structure 303a and the additional third stepped structure 303b; and between the fourth stepped structure 304a and the additional fourth stepped structure 304b.

[0121] The area between adjacent stadium structures (e.g., first stadium structure 301, second stadium structure 302, third stadium structure 303, and fourth stadium structure 304) may include a raised area 340 (also referred to herein as the "peak area"). The raised area 340 may be located, for example, in the first stepped area 115a (…). Figure 1H ) and the second step area 115b ( Figure 1H )between.

[0122] As described above, the conductive contact structure (e.g., the first conductive contact structure 150) Figure 1K , Figure 1L ) and second conductive contact structure ( Figure 1N , Figure 10 Vertical conductive contact 211 Figure 2 Conductive portions may be formed in each layer (e.g., each step 311) of the stacked structure 305 of the microelectronic device structure 300. In some embodiments, one or more of the stadium structures 301, 302, 303, 304 may include a trench structure (e.g., trench structure 160) Figure 1L , Figure 10 Additional slot structures between (e.g., additional slot structure 180) Figure 1L In some embodiments, only one of stadium structures 301, 302, 303, and 304 includes an additional slot structure, while the other stadium structures 301, 302, 303, and 304 only include slot structures. In some embodiments, a stadium structure (e.g., stadium structure 301) having a vertically higher (e.g., in the Z direction) step 311 may correspond to having an additional slot structure 180. Figure 1L The first step area 115a Figure 1N Other stadium structures may correspond to other stepped zones that do not include additional trough structures (e.g., second stepped zone 115b). Figure 1N )).

[0123] As those skilled in the art will understand, although the microelectronic device structure 200 ( Figure 2 ) and microelectronic device structure 300 ( Figure 3 The structures 200 and 300 have been described as having a specific structure, but this disclosure is not limited thereto, and the microelectronic device structures 200 and 300 may have different geometric configurations and orientations.

[0124] Therefore, according to embodiments of the present disclosure, a microelectronic device includes: a stacked structure including an insulating structure vertically intersecting with a conductive structure; a first support pillar structure extending vertically through the stacked structure in a first stepped region, the first stepped region including steps defined at the edges of layers of the insulating and conductive structures; and a second support pillar structure extending vertically through the stacked structure in a second stepped region, the second stepped region including additional steps defined at the edges of additional layers of the insulating and conductive structures, the second support pillar structure having a smaller lateral cross-sectional area than the first support pillar structure.

[0125] Therefore, according to an additional embodiment of the present disclosure, a microelectronic device includes: a stacked structure including a vertically alternating sequence of conductive and insulating structures arranged in layers; an array region including a string of memory cells extending vertically through the stacked structure; a first step region laterally adjacent to the array region and including steps defined at the lateral edges of some of the layers of conductive and insulating structures; a second step region laterally adjacent to the first step region and including additional steps defined at the lateral edges of the others of the layers of conductive and insulating structures; a first conductive contact structure electrically connected to the steps of the first step region; and a second conductive contact structure electrically connected to the additional steps of the second step region, the second conductive contact structure having a larger dimension than the first conductive contact structure.

[0126] Therefore, according to other embodiments of this disclosure, a method of forming a microelectronic device includes: forming pillars comprising channel material in an array region of a stacked structure, the stacked structure comprising a vertically alternating sequence of insulating structures and additional insulating structures; forming an insulating material vertically covering the pillars and vertically covering a stepped region, the stepped region comprising a first stepped region laterally adjacent to the array region and a second stepped region laterally adjacent to the first stepped region; forming a groove extending vertically through the stacked structure; replacing each of the additional insulating structures with a conductive structure through the groove; filling the groove with material to form a groove structure; forming an opening in the array region, each opening in the array region exposing conductive material electrically connected to one of the pillars; forming an additional opening in the first stepped region, each opening individually exposing different conductive structures in the conductive structure; forming conductive material in the opening to form a conductive contact in the array region; and forming conductive material in the additional opening to form a first conductive contact structure in the first stepped region.

[0127] The microelectronic device includes a microelectronic device (e.g., microelectronic device 201) and a microelectronic device structure (e.g., microelectronic device structure 100, 200, 300) formed according to embodiments of the present disclosure. For example, Figure 4 This is a block diagram of an electronic system 403 according to an embodiment of the present disclosure. The electronic system 403 may include, for example, a computer or computer hardware component, a server or other network-connected hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 403 includes at least one memory device 405. Memory device 405 may include, for example, microelectronic device structures previously described herein (e.g., microelectronic device structures 100, 200, 300) or microelectronic devices (e.g., previously referenced...). Figures 1A to 1J , Figure 2 and Figure 3 The described embodiment of the microelectronic device 201. Although the memory device 405 and the electronic signal processor device 407 are depicted as Figure 4 The two (2) separate devices are included in the electronic system 403, but in an additional embodiment, a single (e.g., only one) memory / processor device having the functionality of memory device 405 and electronic signal processor device 407 is included in the electronic system 403. In such embodiments, the memory / processor device may include one or more of the microelectronic device architectures (e.g., one of microelectronic device architectures 100, 200, 300) and microelectronic devices (e.g., microelectronic device 201) previously described herein.

[0128] Electronic system 403 may further include at least one electronic signal processor device 407 (generally referred to as a “microprocessor”). Electronic signal processor device 407 may optionally include one or more embodiments of the microelectronic devices and microelectronic device architectures previously described herein. Electronic system 403 may further include one or more input devices 409 for inputting information into electronic system 403 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 403 may further include one or more output devices 411 for outputting information (e.g., visual or audio output) to a user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 409 and output device 411 may include a single touchscreen device that can be used both to input information into electronic system 403 and to output visual information to a user. Input device 409 and output device 411 may be electrically connected to one or more of memory device 405 and electronic signal processor device 407.

[0129] refer to Figure 5 The present invention describes a processor-based system 500. The processor-based system 500 may include one or more microelectronic devices and microelectronic device structures previously described herein and manufactured according to embodiments of the present disclosure. The processor-based system 500 may be any of a variety of types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 500 may include one or more processors 502, such as microprocessors, to control system functions and request processing within the processor-based system 500. The processors 502 and other sub-components of the processor-based system 500 may include one or more microelectronic devices and microelectronic device structures previously described herein and manufactured according to embodiments of the present disclosure.

[0130] The processor-based system 500 may include a power supply 504 operatively connected to the processor 502. For example, if the processor-based system 500 is a portable system, the power supply 504 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power supply 504 may also include an AC adapter; thus, the processor-based system 500 can be plugged into a wall outlet. For example, the power supply 504 may also include a DC adapter, allowing the processor-based system 500 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0131] Various other devices may be coupled to processor 502 depending on the functions performed by processor-based system 500. For example, user interface 506 may be coupled to processor 502. User interface 506 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. Display 508 may also be coupled to processor 502. Display 508 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 510 may also be coupled to processor 502. RF subsystem / baseband processor 510 may include antennas coupled to RF receivers and RF transmitters (not shown). Communication port 512 or more may also be coupled to processor 502. For example, communication port 512 may be adapted to couple to one or more peripheral devices 514, such as modems, printers, computers, scanners or cameras, or to a network, such as a local area network, a remote local area network, an intranet or the Internet.

[0132] Processor 502 can control processor-based system 500 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 502 to store and facilitate the execution of various programs. For example, processor 502 may be coupled to system memory 516, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. System memory 516 may include volatile memory, non-volatile memory, or combinations thereof. System memory 516 is typically large enough to dynamically store loaded application programs and data. In some embodiments, system memory 516 may include semiconductor devices, such as one or more of the microelectronic devices and microelectronic device architectures previously described herein.

[0133] Processor 502 may also be coupled to non-volatile memory 518, which does not imply that system memory 516 is necessarily volatile. Non-volatile memory 518 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory 516. The size of non-volatile memory 518 is typically chosen to be sufficient to store only the necessary operating system, applications, and fixed data. Furthermore, for example, non-volatile memory 518 may include large-capacity memory such as disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory. Non-volatile memory 518 may include microelectronic devices, such as one or more of the microelectronic devices and microelectronic device architectures described earlier herein.

[0134] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device structure includes: an array region comprising a string of memory cells extending vertically through an alternating vertical sequence of insulating and conductive structures; and a first step region laterally adjacent to the array region, the first step region including first conductive contact structures extending vertically through a dielectric material overlying the first step region, each of the first conductive contact structures being individually electrically connected to a different conductive structure in the conductive structure. Each of the first conductive contact structures includes a conductive liner material in contact with the dielectric material and a conductive material in contact with the conductive liner material. The at least one microelectronic device structure further includes: a second step region laterally adjacent to the first step region, the second step region including second conductive contact structures having a size larger than the first conductive contact structures, the second conductive contact structures extending vertically through the dielectric material, each of the second conductive contact structures being individually electrically connected to an additional conductive structure in the conductive structure. Each of the second conductive contact structures includes: an oxide lining material in contact with a dielectric material; a conductive lining material in contact with the oxide lining material; and a conductive material in contact with the conductive lining material.

[0135] Additional non-limiting example embodiments of this disclosure are described below.

[0136] Example 1: A microelectronic device comprising: a stacked structure including an insulating structure vertically intersecting a conductive structure; a first support pillar structure extending vertically through the stacked structure in a first stepped region, the first stepped region including steps defined at the edges of layers of the insulating and conductive structures; and a second support pillar structure extending vertically through the stacked structure in a second stepped region, the second stepped region including additional steps defined at the edges of additional layers of the insulating and conductive structures, each of the second support pillar structures having a smaller lateral cross-sectional area than each of the first support pillar structures.

[0137] Example 2: The microelectronic device according to Example 1, wherein the first support column structure exhibits an elliptical transverse cross-sectional shape, and the second support column structure exhibits a circular transverse cross-sectional shape.

[0138] Example 3: The microelectronic device according to Example 1 or Example 2 further includes a first conductive contact structure electrically connected to some of the conductive structures in the stacked structure at the step of the first step region.

[0139] Example 4: The microelectronic device according to Example 3 further includes a second conductive contact structure electrically connected to some other conductive structures in the conductive structure of the stacked structure at the additional step in the second step region, each of the second conductive contact structures having a larger lateral dimension than each of the first conductive contact structures.

[0140] Example 5: The microelectronic device according to Example 4, wherein for each of the second conductive contact structures in the second stepped region, the first stepped region comprises four of the first conductive contact structures.

[0141] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein the step of the first step region is located at the additional step that is vertically higher than the second step region.

[0142] Example 7: The microelectronic device according to any one of Examples 1 to 6 further includes an array region that is laterally adjacent to the first stepped region and includes a string of memory cells extending vertically through the stacked structure.

[0143] Example 8: The microelectronic device according to Example 7 further includes a conductive contact electrically connected to a channel region of one of the memory cell strings.

[0144] Example 9: The microelectronic device according to Example 8, wherein the size of the conductive contact is substantially the same as the size of the first conductive contact structure that contacts the step of the first stepped region.

[0145] Example 10: A memory device comprising: a stacked structure including a vertically alternating sequence of conductive and insulating structures arranged in layers; an array region including a string of memory cells extending vertically through the stacked structure; a first step region laterally adjacent to the array region and including steps defined at lateral edges of some of the layers of the conductive and insulating structures; a second step region laterally adjacent to the first step region and including additional steps defined at lateral edges of the others of the layers of the conductive and insulating structures; a first conductive contact structure electrically connected to the steps of the first step region; and a second conductive contact structure electrically connected to the additional steps of the second step region, the second conductive contact structure having a larger dimension than the first conductive contact structure.

[0146] Example 11: The memory device according to Example 10, wherein the diameter of each of the second conductive contact structures is greater than twice the diameter of each of the first conductive contact structures.

[0147] Example 12: The memory device according to Example 10 or Example 11 further includes: a first support pillar structure located in the first stepped area; and a second support pillar structure located in the second stepped area.

[0148] Example 13: The memory device according to Example 12, wherein each of the first support pillar structures has a lateral dimension that is greater than the lateral dimension of each of the second support pillar structures.

[0149] Example 14: The memory device according to Example 12 or Example 13, wherein: the first support column structure individually exhibits an elliptical transverse cross-sectional shape; and the second support column structure individually exhibits a circular transverse cross-sectional shape.

[0150] Example 15: A memory device according to any one of Examples 10 to 14, wherein the lateral centers of some of the first conductive contact structures are laterally aligned with the lateral centers of the others in the first conductive contact structures in a first lateral direction and a second lateral direction.

[0151] Example 16: A memory device according to any one of Examples 10 to 15, wherein the second conductive contact structure is laterally offset from the first conductive contact structure in a first lateral direction and a second lateral direction.

[0152] Example 17: A memory device according to any one of Examples 10 to 16, wherein the stacking structure is divided into block structures that are separate from each other by a slot structure, and each of the block structures is divided into sub-block structures that are separate from each other by an additional slot structure in each of the array region and the first step region.

[0153] Example 18: The memory device according to Example 17, wherein the additional slot structure terminates at the boundary between the first stepped region and the second stepped region.

[0154] Example 19: A memory device according to Example 17 or Example 18, wherein each step in each sub-block structure of the first stepped region is electrically connected to one of the first conductive contact structures.

[0155] Example 20: A memory device according to any one of Examples 10 to 19 further includes a conductive contact in series with the memory cell, the conductive contact having a lateral region substantially the same as the first conductive contact structure.

[0156] Example 21: A memory device according to any one of Examples 10 to 20, further comprising an etch-stop material comprising carbon-doped silicon nitride above the memory cell string in the array region and laterally adjacent to the conductive contact electrically connected to the memory cell string.

[0157] Example 22: A method of forming a microelectronic device, the method comprising: forming pillars including channel material in an array region of a stacked structure, the stacked structure including a vertically alternating sequence of insulating structures and additional insulating structures; forming an insulating material vertically covering the pillars and vertically covering a distributed stepped region, the distributed stepped region including a first stepped region laterally adjacent to the array region and a second stepped region laterally adjacent to the first stepped region; forming a groove extending vertically through the stacked structure; replacing at least a portion of each of the additional insulating structures with a conductive structure through the groove; filling the groove with material to form a groove structure; forming an opening in the array region, each of the openings exposing conductive material electrically connected to one of the pillars; forming an additional opening in the first stepped region, each of the additional openings individually exposing one of the conductive structures; forming conductive material in the opening to form a conductive contact in the array region; and forming conductive material in the additional opening to form a first conductive contact structure in the first stepped region.

[0158] Example 23: The method according to Example 22 further includes forming a second conductive contact structure in the second step region that is electrically connected to the other components of the conductive structure.

[0159] Example 24: According to the method of Example 23, forming the second conductive contact structure includes forming a second conductive contact structure with a diameter approximately twice the diameter of the first conductive contact structure.

[0160] Example 25: The method according to any one of Examples 22 to 24 further includes forming a first support column structure that extends vertically through the stacked structure in the first stepped area.

[0161] Example 26: The method according to Example 25 further includes forming a second support column structure extending vertically through the stacked structure in the second step area, at least one of the second support column structures having a lateral dimension smaller than that of at least one of the first support column structures.

[0162] Example 27: The method according to any of Examples 22 to 26 further includes forming an additional slot structure that extends partially vertically through the stacked structure in each of the array region and the first step region, wherein some laterally adjacent pairs of the first conductive contact structures are laterally separated from each other through one of the additional slot structures.

[0163] Example 28: The method according to Example 27 further includes forming a first support column structure between lateral adjacent pairs of the additional slot structure, the first support column structure extending in the lateral direction of the additional slot structure.

[0164] Example 29: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure including: an array region including a string of memory cells extending vertically through an alternating vertical sequence of insulating and conductive structures; a first step region laterally adjacent to the array region and including a first conductive contact structure extending vertically through a dielectric material covering the first step region, each of the first conductive contact structures being individually connected to a conductive structure. An electrically connected region includes: a conductive liner material in contact with the dielectric material; and a conductive material in contact with the conductive liner material; and a second stepped region laterally adjacent to the first stepped region and including second conductive contact structures each having a larger dimension than each of the first conductive contact structures, the second conductive contact structures extending vertically through the dielectric material and individually electrically connected to another of the conductive structures, each of the second conductive contact structures including: an oxide liner material in contact with the dielectric material; an additional conductive liner material in contact with the oxide liner material; and an additional conductive material in contact with the additional conductive liner material.

[0165] Example 30: The electronic system according to Example 29 further includes: a first support pillar structure that extends vertically through a portion of a vertically alternating sequence of insulating and conductive structures within the first stepped region; and a second support pillar structure that extends vertically through an additional portion of the vertically alternating sequence of insulating and conductive structures within the second stepped region, wherein at least one of the first support pillar structures has a larger lateral dimension than at least one of the second support pillar structures.

[0166] While certain illustrative embodiments have been described in conjunction with drawings, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. In fact, various additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure (such as those claimed herein, including legal equivalents). Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being covered within the scope of this disclosure.

Claims

1. A microelectronic device comprising: A stacked structure, which includes an insulating structure that is vertically intersected with the conductive structure; A first support column structure extends vertically through the stacked structure in a first stepped area, the first stepped area including steps defined at the edges of the layers of the insulating and conductive structures. A second support column structure extends vertically through the stacked structure in a second stepped area, the second stepped area including additional steps at the edges of additional layers of the insulating and conductive structures, each of the second support column structures having a smaller lateral cross-sectional area than each of the first support column structures. A first conductive contact structure electrically connected to some of the conductive structures in the stacked structure at the step of the first stepped area; as well as A second conductive contact structure electrically connected to some other conductive structures in the conductive structure of the stacked structure at the additional step of the second step region, each of the second conductive contact structures having a larger lateral dimension than each of the first conductive contact structures.

2. The microelectronic device according to claim 1, wherein the first support column structure has an elliptical cross-sectional shape, and the second support column structure has a circular cross-sectional shape.

3. The microelectronic device of claim 1, wherein for each of the second conductive contact structures within the second stepped region, the first stepped region comprises four of the first conductive contact structures.

4. The microelectronic device of claim 1, wherein the step of the first step region is located at the additional step that is vertically higher than the second step region.

5. The microelectronic device according to any one of claims 2 to 4, further comprising an array region laterally adjacent to the first stepped region and containing a string of memory cells extending vertically through the stacked structure.

6. The microelectronic device of claim 5, further comprising a conductive contact electrically connected to a channel region of one of the memory cell strings.

7. The microelectronic device of claim 6, wherein the size of the conductive contact is substantially the same as the size of the first conductive contact structure that contacts the step of the first stepped region.

8. A memory device comprising: A stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers; An array region comprising a string of memory cells extending vertically through the stacked structure; The first step region is laterally adjacent to the array region and includes steps at some of the lateral edges of the layers of the conductive structure and the insulating structure. The second step region is laterally adjacent to the first step region and includes additional steps defined at the lateral edges of the other layers of the conductive structure and the insulating structure. A first conductive contact structure is electrically connected to the step in the first stepped region; A second conductive contact structure is electrically connected to the additional step of the second stepped region, and the second conductive contact structure has a larger size than the first conductive contact structure. The first support column structure is located in the first stepped area; and A second support column structure is located in the second stepped area, wherein each of the first support column structures has a lateral dimension that is larger than the lateral dimension of each of the second support column structures.

9. The memory device of claim 8, wherein the diameter of each of the second conductive contact structures is greater than twice the diameter of each of the first conductive contact structures.

10. The memory device according to claim 8, wherein: The first support column structure individually exhibits an elliptical transverse cross-sectional shape; and The second support column structure individually exhibits a circular transverse cross-sectional shape.

11. The memory device of claim 8, wherein the lateral centers of some of the first conductive contact structures are laterally aligned with the lateral centers of the others in the first conductive contact structures in a first lateral direction and a second lateral direction.

12. The memory device of claim 8, wherein the second conductive contact structure is laterally offset from the first conductive contact structure in a first lateral direction and a second lateral direction.

13. The memory device of claim 8, wherein the stacked structure is divided into mutually separate block structures by slot structures, each of the block structures being divided into mutually separate sub-block structures within each of the array region and the first step region by additional slot structures.

14. The memory device of claim 13, wherein the additional slot structure terminates at the boundary between the first stepped region and the second stepped region.

15. The memory device of claim 13, wherein each step in each sub-block structure of the first stepped region is electrically connected to one of the first conductive contact structures.

16. The memory device according to any one of claims 9 to 15, further comprising a conductive contact in series communication with the memory cell, the conductive contact having a lateral region substantially the same as the first conductive contact structure.

17. The memory device according to any one of claims 9 to 15, further comprising an etch-stop material, said etch-stop material comprising carbon-doped silicon nitride above the memory cell string in the array region and laterally adjacent to a conductive contact electrically connected to the memory cell string.

18. A method of forming a microelectronic device, the method comprising: Pillars comprising channel material are formed in an array region of a stacked structure, the stacked structure comprising a vertically alternating sequence of insulating structures and additional insulating structures; An insulating material is formed that is vertically covered on the column and vertically covered on the distributed stepped area, wherein the distributed stepped area includes a first stepped area that is laterally adjacent to the array area and a second stepped area that is laterally adjacent to the first stepped area; Forming a slot that extends vertically through the stacked structure; At least a portion of each of the additional insulating structures is replaced by a conductive structure through the groove; The groove is filled with material to form a groove structure; An opening is formed in the array region, each of the openings exposing a conductive material that is electrically connected to one of the pillars; Additional openings are formed in the first stepped region, each of the additional openings individually exposing one of the conductive structures; Conductive material is formed in the opening to form conductive contacts in the array region; Conductive material is formed in the additional opening to form a first conductive contact structure in the first stepped region; A first support column structure is formed in the first stepped area, extending vertically through the stacked structure; and A second support column structure is formed in the second stepped area, extending vertically through the stacked structure, and at least one of the second support column structures has a lateral dimension smaller than that of at least one of the first support column structures.

19. The method of claim 18, further comprising forming a second conductive contact structure in the second stepped region that is electrically connected to the other of the conductive structure.

20. The method of claim 19, wherein forming the second conductive contact structure comprises forming a second conductive contact structure with a diameter approximately twice the diameter of the first conductive contact structure.

21. The method according to any one of claims 18 to 20, further comprising forming an additional slot structure within each of the array region and the first stepped region, extending partially vertically through the stacked structure, wherein some laterally adjacent pairs of the first conductive contact structures are laterally separated from each other through one of the additional slot structures.

22. The method of claim 21, further comprising forming a first support column structure between lateral adjacent pairs of the additional slot structure, the first support column structure extending in the direction in which the additional slot structure extends laterally.

23. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: An array region comprising a string of memory cells extending vertically through alternating vertical sequences of insulating and conductive structures; A first stepped region, which is laterally adjacent to the array region and includes a first conductive contact structure extending vertically through a dielectric material covering the first stepped region, each of the first conductive contact structures being individually electrically connected to one of the conductive structures and including: A conductive lining material that is in contact with the dielectric material; and A conductive material that is in contact with the conductive lining material; A second stepped region, which is laterally adjacent to the first stepped region and includes second conductive contact structures, each having a larger dimension than each of the first conductive contact structures. Each second conductive contact structure extends vertically through the dielectric material and is individually electrically connected to another of the conductive structures. Each second conductive contact structure includes: An oxide lining material that is in contact with the dielectric material; An additional conductive lining material, which is in contact with the oxide lining material; and Additional conductive material, which is in contact with the additional conductive lining material; A first support column structure, which extends vertically within the first stepped region through portions of the vertically alternating sequence of the insulating and conductive structures; and A second support column structure extends vertically through an additional portion of the vertical alternating sequence of the insulating and conductive structures within the second stepped region, wherein at least one of the first support column structures has a larger lateral dimension than at least one of the second support column structures.

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