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Dual-ported pipelined two level cache system

A cache, cache technology, applied in memory systems, instruments, memory address/allocation/relocation, etc., can solve problems such as long access latency

Inactive Publication Date: 2004-06-16
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Conversely, a large cache memory means it has a long access latency

Method used

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  • Dual-ported pipelined two level cache system
  • Dual-ported pipelined two level cache system
  • Dual-ported pipelined two level cache system

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Embodiment Construction

[0041] A novel cache memory that achieves improved cache storage is provided. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other implementations, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.

[0042]FIG. 1 is a block diagram showing an embodiment of a cache memory 100 in accordance with the teachings of the present invention. FIG. 1 shows that the cache memory 100 includes a first-level (L0) cache memory 110 and a second-level (L1) cache memory 120 . The first-level cache memory 110 , L0 is also referred to as the first-level cache 110 in this specification. The second-level cache memory 120 , L1 is also referred to as the second-level cache 120 i...

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Abstract

A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The on-chip cache memory has two levels. The first level is optimized for low latency and the second level is optimized for capacity. Both levels of cache are pipelined and can support simultaneous dual port accesses. A queuing structure is provided between the first and second level of cache which is used to decouple the faster first level cache from the slower second level cache. The queuing structure is also dual ported. Both levels of cache support non-blocking behavior. When there is a cache miss at one level of cache, both caches can continue to process other cache hits and misses. The first level cache is optimized for integer data. The second level cache can store any data type including floating point. The novel two-level cache system of the present invention provides high performance which emphasizes throughput.

Description

field of invention [0001] The present invention relates generally to the field of electronic data processing devices. More specifically, the invention relates to tuning buffer memory. Background technique [0002] Many computer systems today use cache memory to improve the speed of access to more frequently used data and instructions. A small cache memory can be integrated on the microprocessor chip itself, thereby greatly improving access speed by eliminating the need to access data or instructions from external memory outside the microprocessor chip. [0003] During a normal data load access routine, the microprocessor will first check to see if the required data or instruction resides in the on-chip cache memory. If not, the microprocessor looks at memory that is not on the chip. On-chip memory, known as cache memory, is smaller than main memory. Multiple main memory locations may be mapped into cache memory. Main memory locations or addresses representing the most f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08
CPCG06F12/0897
Inventor 傅伟昌D·A·穆拉G·S·马修斯S·E·塞勒
Owner INTEL CORP