A memory testing apparatus, method, electronic device and storage medium

Abstract

The application discloses a memory testing device, method, electronic equipment and storage medium, and relates to the technical field of computers.The device comprises a field programmable logic gate array module, a memory controller module and a memory module; the field programmable logic gate array module is used for receiving instructions of a testing end and delivering the instructions and test cases to the memory controller module; the memory controller module is used for training and / or testing a memory to be tested according to the instructions and returning training results and / or test results to the field programmable logic gate array module; and the field programmable logic gate array module is further used for receiving the training results and / or test results to obtain analysis results, and sending the training results and / or test results and the analysis results to the testing end.The application can reduce the demand of testing on a hardware environment, reduce the use threshold and reduce the cost.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a memory testing apparatus, method, electronic device, and storage medium. Background Technology

[0002] With the continuous rise and development of cloud computing technology and related derivative technologies and products, the business volume of the internet industry has gradually shown explosive growth. As the physical carrier of virtual data, the demand for server nodes is also increasing day by day.

[0003] Currently, the actual failure rate of servers due to DRAM (Dynamic Random Access Memory) failures, i.e., memory failures, far exceeds our estimated rates. Therefore, maintaining and repairing machines with memory failures consumes significant human and material resources and also has a substantial negative impact on the overall system performance.

[0004] Therefore, we need to improve the reliability of memory modules in the overall system. Memory failures caused by memory module failures actually account for a large proportion of complete system failures. However, since these failures are generally concentrated in the DRAM, they are difficult to observe with the naked eye. Ideally, we need to use corresponding ATE (Automatic Test Equipment) equipment to perform quality testing on the memory and screen out memory modules that may be faulty and cannot be repaired.

[0005] Currently, existing memory testing methods include the following two approaches:

[0006] 1. Perform memory testing by executing the corresponding memory testing program within the operating system. However, this method has a problem: memory testing requires rewriting the data in each cell of memory. If the memory is already being used by the operating system, the operating system will occupy a portion of the memory, and rewriting this portion of the data can lead to unpredictable errors. Therefore, this method cannot achieve full coverage of memory testing.

[0007] 2. Perform memory testing by executing a memory test program within the BIOS (Basic Input Output System). This method tests the memory before the entire system boots up. At this stage, the code operates in the BIOS's ROM (Read-Only Memory), where the memory space is unused, thus enabling full-coverage memory testing. However, this method suffers from low efficiency due to the code residing in ROM, and requires additional support during the BIOS testing phase, increasing development costs.

[0008] Current technologies also combine the two methods mentioned above for memory testing, dividing the memory space into two parts: the memory space used by the operating system is tested through the BIOS, while the memory space used by the non-operating system is tested through the operating system. This achieves full coverage of memory testing while avoiding the low testing efficiency of testing solely through the BIOS. However, this approach requires the same hardware environment as traditional memory testing tools, offering no hardware cost optimization. Furthermore, its logical processing complexity increases, as this technology is still based on traditional memory testing solutions and requires technical support, thus increasing development costs. Additionally, this technology does not optimize the space required for memory testing tools, necessitating a near-complete server system architecture, leading to large footprint, heat dissipation issues, and noise problems. Summary of the Invention

[0009] To address at least one of the problems mentioned in the background art, this application provides a memory testing apparatus, method, electronic device, and storage medium that can reduce the hardware environment requirements for testing, lower the barrier to entry, and reduce costs.

[0010] The specific technical solutions provided in this application are as follows:

[0011] Firstly, a memory testing device is provided, comprising:

[0012] Field-programmable gate array (FPGA) module, memory controller module, and memory module;

[0013] The field-programmable gate array module is used to receive instructions from the test terminal and transmit the instructions and test cases to the memory controller module;

[0014] The memory controller module is used to train and / or test the memory to be tested according to the instructions and return the training results and / or test results to the field programmable gate array module.

[0015] The field-programmable gate array module is also used to receive the training results and / or the test results, analyze them to obtain analysis results, and send the training results and / or the test results and the analysis results to the test terminal.

[0016] Furthermore, the field-programmable gate array module communicates with the memory controller module via the Fast Connect Compute Channel protocol, so that the memory module is visible to the field-programmable gate array module.

[0017] Furthermore, the instructions include calibration instructions, and the field-programmable gate array module is also used to receive calibration instructions from the test end and transmit the calibration instructions and test cases to the memory controller module;

[0018] The memory controller module is also used to train the memory to be tested according to the calibration instructions and return the training results to the field-programmable gate array module;

[0019] The field-programmable gate array module is also used to record training results that meet preset specifications as calibration data for the current memory under test until the next calibration.

[0020] Furthermore, the memory controller module is also used to switch the channel to a high-speed serial computer expansion bus standard channel after calibration is completed.

[0021] Furthermore, the field-programmable gate array module is also used to record the training result that meets the target preset specification as the calibration data of the current memory under test in response to detecting that the link margin in the training result meets the target preset specification.

[0022] The memory controller module is also used to save the calibration data of the current memory under test to the storage unit.

[0023] Furthermore, the instructions also include test instructions;

[0024] After calibration is completed, the field-programmable gate array module is also used to receive test instructions from the test terminal and transmit the test instructions and test cases to the memory controller module.

[0025] After calibration is completed, the memory controller module is also used to test the memory under test through the built-in self-test module of the memory according to the test instructions and return the test results to the field programmable gate array module.

[0026] The field-programmable gate array module is also used to receive the test results, analyze them to obtain analysis results, and send the test results and the analysis results to the test terminal.

[0027] The analysis results describe the fault conditions of the memory under test.

[0028] Furthermore, the field-programmable gate array module is also used to read the temperature data of the temperature control box through an external bus protocol and issue temperature control commands to the temperature control box;

[0029] The out-of-band bus protocol includes at least one of a two-wire serial bus and a high-speed serial computer extension bus standard.

[0030] Secondly, a memory testing method is provided, including:

[0031] The system receives instructions from the test terminal via a field-programmable gate array (FPGA) module and transmits the instructions and test cases to the memory controller module.

[0032] The memory controller module trains and / or tests the memory under test according to the instructions and returns the training results and / or test results to the field-programmable gate array module.

[0033] The field-programmable gate array module receives the training results and / or the test results, analyzes them to obtain analysis results, and sends the training results and / or the test results, along with the analysis results, to the test terminal.

[0034] Thirdly, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the memory testing method.

[0035] Fourthly, a computer-readable storage medium is provided, storing computer-executable instructions for executing the memory testing method described above.

[0036] The embodiments of this application have the following beneficial effects:

[0037] The memory testing apparatus, method, electronic device, and storage medium provided in this application can decouple the hardware requirements of traditional memory testing tools for high-performance CPUs, and at the same time decouple the software support requirements of traditional memory testing tools for AMIs, greatly reducing costs; memory testing can be achieved with only three modules (Field Programmable Gate Array module, memory controller module, and memory module), lowering the high requirements for the hardware environment, reducing heat dissipation requirements, and lowering the usage threshold and cost. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This diagram shows the overall framework of the memory testing apparatus provided in an embodiment of this application.

[0040] Figure 2A detailed frame diagram of a memory testing apparatus according to an embodiment of this application is shown;

[0041] Figure 3 A schematic diagram of the architecture of the MBIST module in a memory controller according to an embodiment of this application is shown;

[0042] Figure 4 This document shows a general flowchart of the memory testing method provided in an embodiment of this application;

[0043] Figure 5 A detailed flowchart of a memory testing method according to an embodiment of this application is shown;

[0044] Figure 6 Exemplary systems that can be used to implement the various embodiments described in this application are shown. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] It should be understood that, in the description of this application, unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0047] Example 1

[0048] This application provides a memory testing device, referring to... Figure 1 This includes: field-programmable gate array (FPGA) modules, memory controller modules, and memory modules.

[0049] The field-programmable gate array (FPGA) module receives instructions from the test terminal and passes the instructions and test cases to the memory controller module. The memory controller module trains and / or tests the memory under test according to the instructions and returns the training results and / or test results to the FPGA module. The FPGA module also receives the training results and / or test results, analyzes them to obtain analysis results, and sends the training results and / or test results and analysis results to the test terminal.

[0050] Specifically, the testing end can be a server or a personal computer, depending on the scale of the testing workload. The testing end sends instructions to the memory testing device. The field-programmable gate array (FPGA) module receives these instructions from the testing end via a network or JTAG (Joint Test Action Group) interface. These instructions can be specific to the memory under test, including but not limited to calibration and test instructions described below. The FPGA module can also store test case patterns required for memory testing and pass the instructions and test cases to the memory controller module. The memory controller module receives and executes the instructions from the FPGA module, performs relevant algorithmic actions on the memory module according to the instructions, and then collects the feedback values ​​from the memory module and sends them back to the FPGA module. The FPGA module collects and analyzes the training results and / or test results returned by the memory controller module, and transmits the raw test data and analysis results to the testing end via a network or JTAG interface. By adopting this technology, the hardware requirements of traditional memory testing tools for high-performance CPUs (Central Processing Units) can be decoupled, as can the software support requirements of traditional memory testing tools for AMIs, greatly reducing costs. Memory testing can be achieved with only three modules (Field Programmable Gate Array module, memory controller module, and memory module), lowering the high hardware environment requirements and heat dissipation requirements, thus reducing the barrier to entry and cost of use.

[0051] The following will be combined with the appendix Figure 2 This embodiment will be further described as follows:

[0052] In some implementations, the field-programmable gate array (FPGA) module and the memory controller module communicate via a fast-connect computing channel protocol, making the memory module visible to the FPGA module.

[0053] In some implementations, the memory controller module is also used to switch the channel to a high-speed serial computer expansion bus standard channel after calibration is complete.

[0054] Specifically, the communication protocol between the Field-Programmable Gate Array (FPGA) module and the Memory Controller module is optional, and communication can be achieved via CXL (Compute Express Link) and PCI-Express (Peripheral Component Interconnect Express). When using the memory testing device for the first time, the communication protocol between the FPGA and Memory Controller modules must first be set to CXL. At this point, the memory module is visible to the FPGA module, allowing for training actions on the memory under test and calibration of the test tool's SI (signal integrity) link. After calibration, the memory module no longer needs to be visible to the FPGA module, and the Memory Controller module can then select the PCIe channel for communication with the FPGA module, continuing interaction through the PCIe channel. This technique achieves hardware decoupling of the memory testing tool using the CXL protocol.

[0055] In some implementations, the instructions include calibration instructions. The field-programmable gate array (FPGA) module is also used to receive calibration instructions from the test end and pass the calibration instructions and test cases to the memory controller module. The memory controller module is also used to train the memory under test according to the calibration instructions and return the training results to the FPGA module. The FPGA module is also used to record the training results that meet the preset specifications as the calibration data of the current memory under test until the next calibration.

[0056] Specifically, the Field-Programmable Gate Array (FPGA) module sends calibration commands to the memory controller module. The link between the two uses the CXL protocol, and the memory module is visible to the FPGA module. The memory controller trains the memory under test according to the calibration commands and returns the training results. The FPGA module executes the calibration based on the returned training results, and only after calibration is completed will the test task be issued. Calibration can be performed on different memory models, and relevant data can be saved and uploaded to the cloud.

[0057] In some implementations, the field-programmable gate array module is also used to record the training result that meets the target preset specification as the calibration data of the current memory under test in response to the detection that the link margin in the training result meets the target preset specification; the memory controller module is also used to save the calibration data of the current memory under test to the storage unit.

[0058] Specifically, the FPGA module also determines whether the link margin obtained from the training results meets the target preset specifications. These target preset specifications are generally the specific preset specifications (spec) of the target manufacturer (such as Intel), which can be set by the parameters in the actual deployment test. If the target preset specifications are not met, it indicates that there is a problem with the testing tool and it needs maintenance; if the margin meets the target preset specifications, the FPGA module will record the calibration data until the current memory under test is recalibrated, and the memory controller module will save it to its RAM (Random Access Memory) or other external non-volatile memory units.

[0059] In some implementations, the instructions also include test instructions. After calibration is complete, the field-programmable gate array (FPGA) module is further configured to receive test instructions from the test terminal and pass the test instructions and test cases to the memory controller module. After calibration is complete, the memory controller module is further configured to perform tests on the memory under test through the built-in self-test module according to the test instructions and return the test results to the FPGA module. The FPGA module is further configured to receive the test results, analyze them to obtain analysis results, and send the test results and analysis results to the test terminal. The analysis results describe the fault conditions of the memory under test.

[0060] Specifically, after calibration, the system can select test items to be performed on the memory under test, including but not limited to Row Hammer, MarchA, MarchX, MarchC, MarchG, and MATS tests. The FPGA module sends test instructions carrying the required test items to the memory controller. The MBIST (memory build-in-self test) module in the memory controller calls the corresponding test algorithm to perform read and write operations on each memory storage unit according to the specific test tasks to be performed. For example, taking the March algorithm mentioned above, the memory controller will read and write 0s and 1s in each memory storage unit according to the physical address of the memory. Then, the comparator module in the memory controller compares the read value with the expected value and returns the result. The FPGA module analyzes the fault status of the memory itself based on the return value and the corresponding algorithm. The fault status includes whether there is a fault or a fault risk. If there is a fault or a fault risk, the specific fault type and fault location will also be described. By adopting this technical approach, the test tool can be decoupled from the software through the memory controller, decoupling the software requirements supported by the AMI and reducing costs.

[0061] Specifically, refer to Figure 3 , Figure 3 This diagram illustrates the architecture of the MBIST module within the memory controller. The MBIST module comprises a physical subsystem, a CXL subsystem, and a memory subsystem. The physical subsystem (PHY Subsystem) includes a PCIe / CXL physical interface for interconnection with the FPGA module. It also includes a RISC-V Core and RISC-V firmware. The memory controller's internal code runs within this RISC-V subsystem, managing and monitoring the chip's basic functions, including but not limited to physical layer training, monitoring the chip's internal health, and temperature. The CXL subsystem includes the CXL Controller, which contains the basic cxl.io and cxl.memory interfaces defined by the CXL protocol. This enables CXL-to-DDR I / O (input / output) conversion for initial system link training and calibration. Similarly, calibration data is stored in the memory controller's RAM or external non-volatile memory. After calibration, this subsystem facilitates instruction transmission from the FPGA via PCIe. It also enables instruction transmission to the MBIST Controller unit. Finally, the main function of the DDR Subsystem is to implement the DDR I / O interface, and at the same time, according to the instructions passed by the CXL Subsystem, to read and write to the specified DDR location, compare, and return the data.

[0062] In some implementations, the field-programmable gate array module is also used to read the temperature data of the temperature control box and issue temperature control commands to the temperature control box via an out-of-band bus protocol; the out-of-band bus protocol includes at least one of a two-wire serial bus and a high-speed serial computer extension bus standard.

[0063] Specifically, the Field Programmable Gate Array (FPGA) module can also handle temperature control functions. The FPGA module can read the temperature data from the temperature control chamber via an I2C two-wire serial bus or a PCIe bus, and issue temperature control commands based on the data, enabling the temperature control chamber to execute the corresponding temperature control. If the FPGA module's resources are exhausted, the temperature control task can be executed through the test terminal, with the FPGA module only handling command transmission and execution.

[0064] In this embodiment, the hardware requirements of traditional memory testing tools for high-performance CPUs can be decoupled, as can the software support requirements of traditional memory testing tools for AMIs, greatly reducing costs. Memory testing can be achieved with only three modules (Field Programmable Gate Array module, memory controller module, and memory module), which lowers the high threshold for hardware environment requirements, reduces heat dissipation requirements, and lowers the threshold and cost of use.

[0065] Example 2

[0066] Corresponding to the above embodiments, this application also provides a memory testing method, referring to... Figure 4 The methods include:

[0067] S1. Receive instructions from the test terminal through the field-programmable gate array module, and pass the instructions and test cases to the memory controller module;

[0068] S2. The memory controller module trains and / or tests the memory under test according to the instructions and returns the training results and / or test results to the field programmable gate array module.

[0069] S3. Receive training results and / or test results through the field-programmable gate array module, analyze them to obtain analysis results, and send the training results and / or test results and analysis results to the test terminal.

[0070] Specifically, the test terminal sends instructions to the memory testing device. The field-programmable gate array (FPGA) module receives these instructions from the test terminal via a network or JTAG interface. These instructions can be specific to the memory under test, including but not limited to calibration and test instructions described below. The FPGA module can also store test case patterns required for memory testing and pass the instructions and test cases to the memory controller module. The memory controller module receives and executes the instructions from the FPGA module, performs relevant algorithmic actions on the memory module according to the instructions, and then collects the feedback values ​​from the memory module and sends them back to the FPGA module. The FPGA module collects and analyzes the training results and / or test results returned by the memory controller module, and transmits the raw test data and analysis results to the test terminal via a network or JTAG interface. By adopting this technology, the hardware requirements of traditional memory testing tools for high-performance CPUs can be decoupled, as can the software support requirements of traditional memory testing tools for AMIs, greatly reducing costs. Memory testing can be achieved with only three modules (Field Programmable Gate Array module, memory controller module, and memory module), lowering the high threshold for hardware environment requirements, reducing heat dissipation requirements, and lowering the usage threshold and cost.

[0071] The following will be combined with the appendix Figure 5 This embodiment will be further described as follows:

[0072] In some implementations, the method further includes:

[0073] 101. The field-programmable gate array (FPGA) module and the memory controller module communicate via the Fast Connect Compute Channel protocol so that the memory module is visible to the FPGA module.

[0074] In some implementations, the instructions include calibration instructions, based on which S1 includes:

[0075] S11. Receive calibration instructions from the test terminal through the field-programmable gate array module, and pass the calibration instructions and test cases to the memory controller module;

[0076] S2 includes:

[0077] S21. The memory controller module trains the memory under test according to the calibration instructions and returns the training results to the field programmable gate array module.

[0078] S3 includes:

[0079] S31. Receive training results through the field-programmable gate array module, and record the training results that meet the preset specifications as the calibration data of the current memory under test until the next calibration.

[0080] In some implementations, the method further includes:

[0081] 201. After calibration, the memory controller module switches the channel to the high-speed serial computer expansion bus standard channel.

[0082] In some implementations, S31 further includes:

[0083] S311. The field-programmable gate array module responds to the detection that the link margin in the training result meets the target preset specification, and records the training result that meets the target preset specification as the calibration data of the current memory to be tested.

[0084] S312. The calibration data of the current memory under test is saved to the storage unit through the memory controller module.

[0085] In some implementations, the instructions include test instructions; therefore, S1 further includes:

[0086] S12. After calibration is completed, the test instructions from the test terminal are received through the field programmable gate array module, and the test instructions and test cases are transmitted to the memory controller module.

[0087] S2 also includes:

[0088] S22. After calibration is completed, the memory controller module tests the memory under test through the built-in self-test module of the memory according to the test instructions and returns the test results to the field programmable gate array module.

[0089] S3 also includes:

[0090] S32. Receive test results through the field-programmable gate array module, analyze them to obtain analysis results, and send the test results and analysis results to the test terminal.

[0091] The analysis results describe the fault conditions of the memory under test.

[0092] In some implementations, the method further includes:

[0093] The temperature data of the temperature control box is read by the field-programmable gate array module via an external bus protocol, and temperature control commands are issued to the temperature control box.

[0094] The out-of-band bus protocol includes at least one of a two-wire serial bus and a high-speed serial computer extension bus standard.

[0095] It should be noted that the terms "S1," "S2," etc., are used only for descriptive purposes and do not specifically refer to the order or sequence, nor are they intended to limit this application. They are merely for the convenience of describing the method of this application and should not be construed as indicating the sequential order of the steps. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0096] For specific limitations regarding the memory testing methods described above, please refer to the relevant limitations on memory testing devices mentioned above, so they will not be repeated here.

[0097] Example 3

[0098] Corresponding to the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor can implement the above memory testing method when executing the program.

[0099] like Figure 6 As shown, in some embodiments, the system can serve as any of the aforementioned electronic devices for memory testing methods in each of the described embodiments. In some embodiments, the system may include one or more computer-readable media (e.g., system memory or NVM / storage device) having instructions and one or more processors (e.g., one or more processors) coupled to the one or more computer-readable media and configured to execute the instructions to implement the module and thus perform the actions described in this application.

[0100] In one embodiment, the system control module may include any suitable interface controller to provide any suitable interface to at least one of the processors(s) and / or any suitable device or component communicating with the system control module.

[0101] The system control module may include a memory controller module to provide an interface to the system memory. The memory controller module may be a hardware module, a software module, and / or a firmware module.

[0102] System memory can be used, for example, to load and store data and / or instructions for the system. In one embodiment, system memory may include any suitable volatile memory, such as suitable DRAM. In some embodiments, system memory may include Double Data Rate Type Quad Synchronous Dynamic Random Access Memory (DDR4 SDRAM).

[0103] In one embodiment, the system control module may include one or more input / output (I / O) controllers to provide interfaces to the NVM / storage device and (one or more) communication interfaces.

[0104] For example, an NVM / storage device can be used to store data and / or instructions. An NVM / storage device may include any suitable non-volatile memory (e.g., flash memory) and / or may include any suitable (one or more) non-volatile storage devices (e.g., one or more hard disk drives (HDDs), one or more optical disc drives (CDs), and / or one or more digital universal optical disc (DVD) drives).

[0105] NVM / storage devices may include storage resources that are physically part of a device on which the system is mounted, or that can be accessed by the device without necessarily being part of it. For example, an NVM / storage device may be accessed over a network via one or more communication interfaces.

[0106] One or more communication interfaces may provide the system with an interface to communicate over one or more networks and / or with any other suitable device. The system may wirelessly communicate with one or more components of a wireless network in accordance with any of the standards and / or protocols in one or more wireless network standards and / or protocols.

[0107] In one embodiment, at least one of the processors may be logically packaged with one or more controllers of the system control module (e.g., a memory controller module). In one embodiment, at least one of the processors may be logically packaged with one or more controllers of the system control module to form a system-in-package (SiP). In one embodiment, at least one of the processors may be integrated with the logic of one or more controllers of the system control module on the same die. In one embodiment, at least one of the processors may be integrated with the logic of one or more controllers of the system control module on the same die to form a system-on-a-chip (SoC).

[0108] In various embodiments, the system may be, but is not limited to, a server, workstation, desktop computing device, or mobile computing device (e.g., laptop computing device, handheld computing device, tablet computer, netbook, etc.). In various embodiments, the system may have more or fewer components and / or different architectures. For example, in some embodiments, the system includes one or more cameras, a keyboard, a liquid crystal display (LCD) screen (including a touchscreen display), a non-volatile memory port, multiple antennas, a graphics chip, an application-specific integrated circuit (ASIC), and a speaker.

[0109] It should be noted that this application can be implemented in software and / or a combination of software and hardware, for example, using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In one embodiment, the software program of this application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium, such as RAM memory, magnetic or optical drives, floppy disks, and similar devices. Furthermore, some steps or functions of this application can be implemented in hardware, for example, as circuitry that cooperates with a processor to perform the various steps or functions.

[0110] Furthermore, a portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0111] Communication media include media through which communication signals containing, for example, computer-readable instructions, data structures, program modules, or other data are transmitted from one system to another. Communication media can include guided transmission media (such as cables and wires (e.g., optical fibers, coaxial cables, etc.)) and wireless (unguided transmission) media capable of propagating energy waves, such as sound, electromagnetic, RF, microwave, and infrared. Computer-readable instructions, data structures, program modules, or other data can be embodied as modulated data signals in, for example, wireless media (such as carrier waves or similar mechanisms embodied as part of spread spectrum technology). The term "modulated data signal" refers to a signal whose one or more characteristics are altered or set in a manner that encodes information in the signal. Modulation can be analog, digital, or a hybrid modulation technique.

[0112] Herein, one embodiment of this application includes an apparatus comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the apparatus is triggered to run a method and / or technical solution based on the foregoing embodiments of this application.

[0113] Example 4

[0114] Corresponding to the above embodiments, this application also provides a computer-readable storage medium storing computer-executable instructions for executing a memory testing method.

[0115] In this embodiment, a computer-readable storage medium may include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. For example, a computer-readable storage medium includes, but is not limited to, volatile memories such as random access memory (RAM, DRAM, SRAM); and non-volatile memories such as flash memory, various read-only memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic / ferroelectric memories (MRAM, FeRAM); and magnetic and optical storage devices (hard disks, magnetic tapes, CDs, DVDs); or other currently known media or those developed hereafter capable of storing computer-readable information / data for use by a computer system.

[0116] Although preferred embodiments have been described in this application, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of this application.

[0117] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A memory testing apparatus, characterized by comprising: include: Field-programmable gate array (FPGA) module, memory controller module, and memory module; The field-programmable gate array module communicates with the memory controller module via the Fast Connect Compute Channel protocol, so that the memory module is visible to the field-programmable gate array module; The field-programmable gate array (FPGA) module is used to receive instructions from the test terminal and transmit the instructions and test cases to the memory controller module; wherein, the instructions include calibration instructions, the FPGA module is also used to receive calibration instructions from the test terminal and transmit the calibration instructions and test cases to the memory controller module; wherein, the instructions also include test instructions, and after calibration is completed, the FPGA module is also used to receive test instructions from the test terminal and transmit the test instructions and test cases to the memory controller module; The memory controller module is used to train and / or test the memory under test according to the instructions and return the training results and / or test results to the field-programmable gate array module; wherein, the memory controller module is also used to train the memory under test according to the calibration instructions and return the training results to the field-programmable gate array module; after calibration is completed, the memory controller module is also used to switch the channel to a high-speed serial computer extended bus standard channel, and test the memory under test through the built-in self-test module according to the test instructions and return the test results to the field-programmable gate array module; The field-programmable gate array (FPGA) module is further configured to receive the training results and / or the test results, analyze them to obtain analysis results, and send the training results and / or the test results and the analysis results to the test terminal; wherein, the FPGA module is further configured to record training results that meet preset specifications as calibration data for the current memory under test until the next calibration; after calibration is completed, the FPGA module is further configured to receive the test results, analyze them to obtain analysis results, and send the test results and the analysis results to the test terminal, wherein the analysis results describe the fault condition of the memory under test.

2. The memory testing apparatus according to claim 1, characterized in that, The field-programmable gate array module is also used to record the training result that meets the target preset specification as the calibration data of the current memory under test in response to detecting that the link margin in the training result meets the target preset specification. The memory controller module is also used to save the calibration data of the current memory under test to the storage unit.

3. The memory testing apparatus according to claim 1, characterized in that, The field-programmable gate array module is also used to read the temperature data of the temperature control box through an external bus protocol and issue temperature control commands to the temperature control box. The out-of-band bus protocol includes at least one of a two-wire serial bus and a high-speed serial computer extension bus standard.

4. A memory testing method, based on the apparatus according to any one of claims 1-3, characterized in that, include: The system receives instructions from the test terminal via a field-programmable gate array (FPGA) module and transmits the instructions and test cases to the memory controller module. The memory controller module trains and / or tests the memory under test according to the instructions and returns the training results and / or test results to the field-programmable gate array module. The field-programmable gate array module receives the training results and / or the test results, analyzes them to obtain analysis results, and sends the training results and / or the test results, along with the analysis results, to the test terminal.

5. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the memory testing method as described in claim 4.

6. A computer-readable storage medium storing computer-executable instructions, characterized in that, The computer-executable instructions are used to execute the memory testing method of claim 4.

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