Epitaxial layer manufacturing method, epitaxial layer and super junction power device with wide process window

Abstract

The present application relates to a method for manufacturing an epitaxial layer, an epitaxial layer and a super-junction power device with a wide process window. The present application comprises providing an N-type substrate with a high doping concentration, forming a first epitaxial layer, forming a second epitaxial layer, defining the positions of N-type columns and P-type columns, etching to form a first empty trench, forming a silicon dioxide column, forming a first silicon dioxide column with a second barrier layer on the top and a second silicon dioxide column with the second barrier layer on the top being etched away, forming a second empty trench, growing an N-type semiconductor to fill the second empty trench, the N-type semiconductor in the second empty trench forming an N-type column, forming a third barrier layer, selectively etching the third barrier layer, etching to form a third empty trench, growing a P-type semiconductor to fill the third empty trench, the P-type semiconductor in the third empty trench forming a P-type column, grinding and removing the third barrier layer, and the P-type columns and the N-type columns being distributed at intervals. The present application ensures that the total amount of N-type impurities is equal to the total amount of P-type impurities.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to epitaxial layer manufacturing methods, epitaxial layers, and superjunction power devices with wide process windows. Background Technology

[0002] Superjunction power MOSFETs are power devices that achieve charge balance at breakdown voltage by using N-pillars and P-pillars spaced apart. Their on-resistance is significantly lower than that of traditional power devices. With the development of superjunction power MOSFETs, in pursuit of even lower on-resistance, cell widths are becoming increasingly smaller, and the doping concentration of the P-pillars and N-pillars is also increasing. Process variations under large cell widths, when applied to small cell widths, cause the breakdown voltage of small-cell-width superjunction power MOSFETs to lose its suitable process window.

[0003] Specifically, the main process variations in superjunction power MOSFETs produced by traditional trench filling processes originate from the width and angle of the etched deep trenches. The traditional trench filling process is as follows: First, a highly doped N-type substrate is provided, and a lightly doped N-type semiconductor is grown from bottom to top on the surface of the N-type substrate to form an N-type epitaxial layer. Second, a barrier layer is formed on the upper surface of the N-type epitaxial layer, followed by selective etching of the barrier layer, and then etching of the N-type epitaxial layer to form multiple trenches that are wider at the top and narrower at the bottom. The N-type epitaxial layers between adjacent trenches form the N-type pillars of the superjunction power MOSFET device. Third, P-type semiconductors are grown and filled into the trapezoidal trenches. The P-type semiconductors within the trenches form the P-type pillars of the superjunction power MOSFET device. Then, the front side of the wafer is ground down to the barrier layer, and finally, the barrier layer is removed. In summary, the width and angle of the etched deep trench directly determine the morphology of the P-type pillars. If the etch width is too large, the total amount of N-type impurities will inevitably be less than the total amount of P-type impurities. If the etch width is too small, the total amount of N-type impurities will inevitably be greater than the total amount of P-type impurities. The different etch deviations between different wafers cannot ensure that the total amount of N-type impurities is equal to the total amount of P-type impurities, resulting in significant differences in electrical parameters between different wafers.

[0004] To solve the above-mentioned process challenges, a new manufacturing process is needed to ensure that the total amount of N-type impurities equals the total amount of P-type impurities. Summary of the Invention

[0005] To this end, the present invention provides an epitaxial layer manufacturing method, an epitaxial layer, and a superjunction power device with a wide process window. By utilizing the characteristic that the deep trenches within the same wafer are exactly the same, it ensures that the N-type pillars and P-type pillars have exactly the same shape. When the N-type pillars and P-type pillars have exactly the same shape, even if there are large deviations in the width and angle of the etched deep trenches, it will not affect the charge balance of the superjunction power device.

[0006] To solve the above-mentioned technical problems, the present invention provides an epitaxial layer manufacturing method, comprising the following steps: Step 1: Provide a highly doped N-type substrate, grow a low-doped N-type semiconductor on one side of the N-type substrate to form a first epitaxial layer, the side of the N-type substrate away from the first epitaxial layer is the back side of the wafer, and the side of the first epitaxial layer away from the N-type substrate is a first plane; Step 2: Grow an N-type semiconductor on the first plane to form a second epitaxial layer. The side of the second epitaxial layer away from the first epitaxial layer is the front side of the wafer. Step 3: Form a first barrier layer on the front side of the wafer, and then selectively etch the first barrier layer to define the positions of the N-type pillars and the P-type pillars; Step 4: Etch the front side of the wafer to form multiple identical, parallel first empty trenches, the bottom of which is in contact with the first epitaxial layer. Step 5: Deposit silicon dioxide on the front side of the wafer to fill the first empty trench and form silicon dioxide pillars located in the first empty trench. Then etch away the silicon dioxide layer and the first barrier layer on the front side of the wafer, leaving the silicon dioxide pillars in the first empty trench. Step 6: A second barrier layer is formed on the front side of the wafer, and then the second barrier layer is selectively etched to form a first silicon dioxide pillar with the second barrier layer on top and a second silicon dioxide pillar with the top second barrier layer etched away; wherein the first silicon dioxide pillar and the second silicon dioxide pillar are alternately distributed; Step 7: Etch away the second silicon dioxide pillar and form a second empty trench, so that the first silicon dioxide pillar and the second empty trench are alternately distributed; Step 8: Grow an N-type semiconductor on the front side of the wafer to fill the second empty trench. The N-type semiconductor in the second empty trench constitutes the N-type pillar of the superjunction power device. Then grind the front side of the wafer down to the second barrier layer. Next, remove the second barrier layer on top of the first silicon dioxide pillar so that the N-type pillar and the first silicon dioxide pillar are spaced apart. Step 9: Form a third barrier layer on the front side of the wafer, and then selectively etch the third barrier layer so that the third barrier layer at the top of the first silicon dioxide pillar is etched away, while retaining the third barrier layer at the top of the N-type pillar. Step 10: Etch away the first silicon dioxide pillar and form a third empty trench, so that the N-type pillars with a third barrier layer on top are alternately distributed with the third empty trench; Step 11: Grow a P-type semiconductor on the front side of the wafer to fill the third empty trench. The P-type semiconductor in the third empty trench constitutes the P-type pillar of the superjunction power device. Then grind the front side of the wafer down to the third barrier layer. Next, remove the third barrier layer. The P-type pillars and the N-type pillars are distributed alternately.

[0007] In one embodiment of the present invention, the doping concentration of the N-type impurity in the second epitaxial layer is lower than the doping concentration of the N-type impurity in the first epitaxial layer and the N-type pillar.

[0008] In one embodiment of the present invention, the second epitaxial layer is an intrinsic semiconductor.

[0009] In one embodiment of the present invention, both the second barrier layer and the third barrier layer are made of silicon nitride.

[0010] This invention provides a method for manufacturing an epitaxial layer, comprising the following steps: Step 1: Provide a highly doped N-type substrate, grow a low-doped N-type semiconductor on one side of the N-type substrate to form a first epitaxial layer, the side of the N-type substrate away from the first epitaxial layer is the back side of the wafer, and the side of the first epitaxial layer away from the N-type substrate is a first plane; Step 2: Grow an N-type semiconductor on the first plane to form a second epitaxial layer. The side of the second epitaxial layer away from the first epitaxial layer is the front side of the wafer. Step 3: Form a first barrier layer on the front side of the wafer, and then selectively etch the first barrier layer to define the positions of the N-type pillars and the P-type pillars; Step 4: Etch the front side of the wafer to form multiple identical, parallel first empty trenches, the bottom of which is in contact with the first epitaxial layer. Step 5: Deposit silicon dioxide on the front side of the wafer to fill the first empty trench and form silicon dioxide pillars located in the first empty trench. Then etch away the silicon dioxide layer and the first barrier layer on the front side of the wafer, leaving the silicon dioxide pillars in the first empty trench. Step 6: A second barrier layer is formed on the front side of the wafer, and then the second barrier layer is selectively etched to form a first silicon dioxide pillar with the second barrier layer on top and a second silicon dioxide pillar with the top second barrier layer etched away; wherein the first silicon dioxide pillar and the second silicon dioxide pillar are alternately distributed; Step 7: Etch away the second silicon dioxide pillar and form a second empty trench, so that the first silicon dioxide pillar and the second empty trench are alternately distributed; Step 8: Grow a P-type semiconductor on the front side of the wafer to fill the second empty trench. The P-type semiconductor in the second empty trench constitutes the P-type pillar of the superjunction power device. Then grind the front side of the wafer down to the second barrier layer. Next, remove the second barrier layer on top of the first silicon dioxide pillar. The P-type pillars and the first silicon dioxide pillars are distributed alternately. Step 9: Form a third barrier layer on the front side of the wafer, and then selectively etch the third barrier layer so that the third barrier layer at the top of the first silicon dioxide pillar is etched away, while retaining the third barrier layer at the top of the P-type pillar. Step 10: Etch away the first silicon dioxide pillar and form a third empty trench, so that the P-shaped pillars with a third barrier layer on top are alternately distributed with the third empty trench; Step 11: An N-type semiconductor is grown on the front side of the wafer to fill the third empty trench. The N-type semiconductor in the third empty trench constitutes the N-type pillar of the superjunction power device. Then, the front side of the wafer is ground down to the third barrier layer. Next, the third barrier layer is removed. The P-type pillars and the N-type pillars are distributed alternately.

[0011] This invention provides an epitaxial layer, which is manufactured by the epitaxial layer manufacturing method described above.

[0012] The present invention provides a superjunction power device with a wide process window, including the aforementioned epitaxial layer.

[0013] The technical solution of the present invention has the following advantages compared with the prior art: The epitaxial layer manufacturing method, epitaxial layer, and superjunction power device with a wide process window described in this invention utilize the characteristic that the deep trenches within the same wafer are identical, ensuring that the N-type pillars and P-type pillars have identical shapes. When the N-type pillars and P-type pillars have identical shapes, even if there are large deviations in the width and angle of the etched deep trenches, it will not affect the charge balance of the superjunction power device. This invention reduces the impact of deviations in the doping concentration of the N-type epitaxial layer on the N-type pillars in traditional processes. Because there is a second epitaxial layer between the N-type pillars and P-type pillars, the epitaxy of this invention can have a normal thermal process, making device design more flexible and convenient. In contrast, traditional trench filling processes must avoid the thermal process causing impurities to diffuse between the N-type pillars and P-type pillars, which would increase the on-resistance. Attached Figure Description

[0014] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0015] Figure 1 This is a schematic cross-sectional view of the first epitaxial layer formed in step one of Embodiment 1 of the present invention.

[0016] Figure 2 This is a schematic cross-sectional view of the second epitaxial layer formed in step two of Embodiment 1 of the present invention.

[0017] Figure 3 This is a cross-sectional structural diagram of step three of embodiment 1 of the present invention, which shows the formation of the first barrier layer.

[0018] Figure 4 This is a schematic cross-sectional view of the first hollow groove formed in step four of embodiment 1 of the present invention.

[0019] Figure 5 This is a schematic cross-sectional view of the silicon dioxide pillar formed in step five of Embodiment 1 of the present invention.

[0020] Figure 6 This is a cross-sectional structural diagram of step six, forming the second barrier layer, in Embodiment 1 of the present invention.

[0021] Figure 7 This is a schematic cross-sectional view of the second silicon dioxide pillar etched to remove the top second barrier layer in step seven of Embodiment 1 of the present invention, forming an empty trench.

[0022] Figure 8 This is a schematic cross-sectional view of the N-shaped column formed in step eight of embodiment 1 of the present invention.

[0023] Figure 9 This is a cross-sectional structural diagram of step nine, forming the third barrier layer, in Embodiment 1 of the present invention.

[0024] Figure 10 This is a schematic cross-sectional view of the silicon dioxide pillar being etched away in step ten of Embodiment 1 of the present invention.

[0025] Figure 11 This is a schematic cross-sectional view of the N-shaped column formed in step eleven of Embodiment 1 of the present invention.

[0026] Explanation of reference numerals in the instruction manual: 1. N-type substrate; 2. First epitaxial layer; 3. Second epitaxial layer; 4. First barrier layer; 5a. First empty trench; 5b. Second empty trench; 5c. Third empty trench; 6. First silicon dioxide pillar; 7. Second silicon dioxide pillar; 8. Second barrier layer; 9. P-type pillar; 10. Third barrier layer; 11. N-type pillar. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0028] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0029] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0030] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0031] Example 1 This embodiment provides a method for manufacturing an epitaxial layer, including the following steps: Step 1: As Figure 1 As shown, a highly doped N-type substrate 1 is provided, and a low-doped N-type semiconductor is grown on one side of the N-type substrate 1 to form a first epitaxial layer 2. The side of the N-type substrate 1 away from the first epitaxial layer 2 is the back side of the wafer, and the side of the first epitaxial layer 2 away from the N-type substrate 1 is a first plane. Step Two: As Figure 2 As shown, an N-type semiconductor is grown on the first plane to form a second epitaxial layer 3. The side of the second epitaxial layer 3 away from the first epitaxial layer 2 is the front side of the wafer. Step 3: As Figure 3 As shown, a first barrier layer 4 is formed on the front side of the wafer, and then the first barrier layer 4 is selectively etched to define the positions of the N-type pillars and the P-type pillars. Step Four: As Figure 4 As shown, etching is performed on the front side of the wafer to form multiple identical, parallel first empty trenches 5a, the bottom of which is in contact with the first epitaxial layer 2. Step 5: As Figure 5As shown, silicon dioxide is deposited on the front side of the wafer to fill the first empty trench 5a, forming a first silicon dioxide pillar 6 and a second silicon dioxide pillar 7 located in the first empty trench 5a. Then, the silicon dioxide layer and the first barrier layer 4 on the front side of the wafer are etched away, leaving the first silicon dioxide pillar 6 and the second silicon dioxide pillar 7 in the first empty trench 5a. Step Six: As Figure 6 As shown, a second barrier layer 8 is formed on the front side of the wafer, and then the second barrier layer 8 is selectively etched to form a first silicon dioxide pillar 6 with the second barrier layer 8 on top and a second silicon dioxide pillar 7 with the top second barrier layer 8 etched away; wherein the first silicon dioxide pillar 6 and the second silicon dioxide pillar 7 are alternately distributed. Step Seven: As Figure 7 As shown, the second silicon dioxide pillar 7 is etched away, and a second empty trench 5b is formed, so that the first silicon dioxide pillar 6 and the second empty trench 5b are alternately distributed; Step 8: As Figure 8 As shown, a P-type semiconductor is grown on the front side of the wafer to fill the second empty trench 5b that appeared in step seven. The P-type semiconductor in the second empty trench 5b constitutes the P-type pillar 9 of the superjunction power device. Then, the front side of the wafer is ground down to the second barrier layer 8. Next, the second barrier layer 8 on top of the first silicon dioxide pillar 6 is removed, so that the P-type pillar 9 and the first silicon dioxide pillar 6 are spaced apart. Step Nine: As Figure 9 As shown, a third barrier layer 10 is formed on the front side of the wafer, and then the third barrier layer 10 is selectively etched so that the third barrier layer 10 at the top of the first silicon dioxide pillar 6 is etched away, while the third barrier layer 10 at the top of the P-type pillar 9 is retained. Step 10: As Figure 10 As shown, the first silicon dioxide pillar 6 is etched away, and a third empty trench 5c is formed, so that the P-type pillar 9 with the third barrier layer 10 on the top and the third empty trench 5c are alternately distributed. Step 11: As Figure 11 As shown, an N-type semiconductor is grown on the front side of the wafer to fill the third empty trench 5c that appeared in step ten. The N-type semiconductor in the third empty trench 5c constitutes the N-type pillar 11 of the superjunction power device. Then, the front side of the wafer is ground down to the third barrier layer 10. Next, the third barrier layer 10 is removed. The P-type pillar 9 and the N-type pillar 11 are distributed alternately.

[0032] Optionally, the doping concentration of the N-type impurities in the second epitaxial layer 3 is lower than the doping concentration of the N-type impurities in the first epitaxial layer 2 and the N-type pillar 11.

[0033] The N-type impurity doping concentration of the N-type column 11 is the same as the P-type impurity doping concentration of the P-type column 9.

[0034] Optionally, the second epitaxial layer 3 is an intrinsic semiconductor.

[0035] Both the second barrier layer 8 and the third barrier layer 10 are made of silicon nitride.

[0036] Example 2 This embodiment provides an epitaxial layer manufacturing method. Compared with Embodiment 1, this embodiment swaps the manufacturing order of the N-type pillar 9 and the P-type pillar 11 in Embodiment 1.

[0037] Using the epitaxial layer fabrication method of Example 1 or Example 2, deep trenches corresponding to N-type pillars 11 and P-type pillars 9 are simultaneously etched, making the deep trenches corresponding to N-type pillars 11 and P-type pillars 9 identical. Then, N-type pillars 11 and P-type pillars 9 are fabricated step-by-step, making their shapes identical. Furthermore, the N-type impurity doping concentration of N-type pillars 11 is the same as the P-type impurity doping concentration of P-type pillars 9. Therefore, even if there are significant deviations in the width and angle of the deep trenches, the total amount of N-type impurities in N-type pillars 11 and P-type impurities in P-type pillars 9 will remain the same, without affecting the charge balance of the superjunction power device, i.e., without adversely affecting the device's breakdown voltage. Using the above epitaxial layer fabrication method, a superjunction power device with a wide process window corresponding to the epitaxial layer can be fabricated.

[0038] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for manufacturing an epitaxial layer, characterized in that, The steps include the following: Step 1: Provide a highly doped N-type substrate, grow a low-doped N-type semiconductor on one side of the N-type substrate to form a first epitaxial layer, the side of the N-type substrate away from the first epitaxial layer is the back side of the wafer, and the side of the first epitaxial layer away from the N-type substrate is a first plane; Step 2: Grow an N-type semiconductor on the first plane to form a second epitaxial layer. The side of the second epitaxial layer away from the first epitaxial layer is the front side of the wafer. Step 3: Form a first barrier layer on the front side of the wafer, and then selectively etch the first barrier layer to define the positions of the N-type pillars and the P-type pillars; Step 4: Etch the front side of the wafer to form multiple identical, parallel first empty trenches, the bottom of which is in contact with the first epitaxial layer. Step 5: Deposit silicon dioxide on the front side of the wafer to fill the first empty trench and form silicon dioxide pillars located in the first empty trench. Then etch away the silicon dioxide layer and the first barrier layer on the front side of the wafer, leaving the silicon dioxide pillars in the first empty trench. Step 6: A second barrier layer is formed on the front side of the wafer, and then the second barrier layer is selectively etched to form a first silicon dioxide pillar with the second barrier layer on top and a second silicon dioxide pillar with the top second barrier layer etched away; wherein the first silicon dioxide pillar and the second silicon dioxide pillar are alternately distributed; Step 7: Etch away the second silicon dioxide pillar and form a second empty trench, so that the first silicon dioxide pillar and the second empty trench are alternately distributed; Step 8: Grow an N-type semiconductor on the front side of the wafer to fill the second empty trench. The N-type semiconductor in the second empty trench constitutes the N-type pillar of the superjunction power device. Then grind the front side of the wafer down to the second barrier layer. Next, remove the second barrier layer on top of the first silicon dioxide pillar so that the N-type pillar and the first silicon dioxide pillar are spaced apart. Step 9: Form a third barrier layer on the front side of the wafer, and then selectively etch the third barrier layer so that the third barrier layer at the top of the first silicon dioxide pillar is etched away, while retaining the third barrier layer at the top of the N-type pillar. Step 10: Etch away the first silicon dioxide pillar and form a third empty trench, so that the N-type pillars with a third barrier layer on top are alternately distributed with the third empty trench; Step 11: Grow a P-type semiconductor on the front side of the wafer to fill the third empty trench. The P-type semiconductor in the third empty trench constitutes the P-type pillar of the superjunction power device. Then grind the front side of the wafer down to the third barrier layer. Next, remove the third barrier layer. The P-type pillars and the N-type pillars are distributed alternately.

2. The epitaxial layer manufacturing method according to claim 1, characterized in that, The doping concentration of the N-type impurity in the second epitaxial layer is lower than that in the first epitaxial layer and the N-type pillar.

3. The epitaxial layer manufacturing method according to claim 1, characterized in that, The second epitaxial layer is an intrinsic semiconductor.

4. The epitaxial layer manufacturing method according to claim 1, characterized in that, Both the second barrier layer and the third barrier layer are made of silicon nitride.

5. A method for manufacturing an epitaxial layer, characterized in that, The steps include the following: Step 1: Provide a highly doped N-type substrate, grow a low-doped N-type semiconductor on one side of the N-type substrate to form a first epitaxial layer, the side of the N-type substrate away from the first epitaxial layer is the back side of the wafer, and the side of the first epitaxial layer away from the N-type substrate is a first plane; Step 2: Grow an N-type semiconductor on the first plane to form a second epitaxial layer. The side of the second epitaxial layer away from the first epitaxial layer is the front side of the wafer. Step 3: Form a first barrier layer on the front side of the wafer, and then selectively etch the first barrier layer to define the positions of the N-type pillars and the P-type pillars; Step 4: Etch the front side of the wafer to form multiple identical, parallel first empty trenches, the bottom of which is in contact with the first epitaxial layer. Step 5: Deposit silicon dioxide on the front side of the wafer to fill the first empty trench and form silicon dioxide pillars located in the first empty trench. Then etch away the silicon dioxide layer and the first barrier layer on the front side of the wafer, leaving the silicon dioxide pillars in the first empty trench. Step 6: A second barrier layer is formed on the front side of the wafer, and then the second barrier layer is selectively etched to form a first silicon dioxide pillar with the second barrier layer on top and a second silicon dioxide pillar with the top second barrier layer etched away; wherein the first silicon dioxide pillar and the second silicon dioxide pillar are alternately distributed; Step 7: Etch away the second silicon dioxide pillar and form a second empty trench, so that the first silicon dioxide pillar and the second empty trench are alternately distributed; Step 8: Grow a P-type semiconductor on the front side of the wafer to fill the second empty trench. The P-type semiconductor in the second empty trench constitutes the P-type pillar of the superjunction power device. Then grind the front side of the wafer down to the second barrier layer. Next, remove the second barrier layer on top of the first silicon dioxide pillar. The P-type pillars and the first silicon dioxide pillars are distributed alternately. Step 9: Form a third barrier layer on the front side of the wafer, and then selectively etch the third barrier layer so that the third barrier layer at the top of the first silicon dioxide pillar is etched away, while retaining the third barrier layer at the top of the P-type pillar. Step 10: Etch away the first silicon dioxide pillar and form a third empty trench, so that the P-shaped pillars with a third barrier layer on top are alternately distributed with the third empty trench; Step 11: An N-type semiconductor is grown on the front side of the wafer to fill the third empty trench. The N-type semiconductor in the third empty trench constitutes the N-type pillar of the superjunction power device. Then, the front side of the wafer is ground down to the third barrier layer. Next, the third barrier layer is removed. The P-type pillars and the N-type pillars are distributed alternately.

6. The epitaxial layer manufacturing method according to claim 5, characterized in that, The doping concentration of the N-type impurity in the second epitaxial layer is lower than that in the first epitaxial layer and the N-type pillar.

7. The epitaxial layer manufacturing method according to claim 5, characterized in that, The second epitaxial layer is an intrinsic semiconductor.

8. The epitaxial layer manufacturing method according to claim 5, characterized in that, Both the second barrier layer and the third barrier layer are made of silicon nitride.

9. An epitaxial layer, characterized in that, It is manufactured by the epitaxial layer manufacturing method according to any one of claims 1-8.

10. A superjunction power device with a wide process window, characterized in that, Includes the epitaxial layer as described in claim 9.

Images