Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; the substrate comprises a substrate formed with a shallow trench defining an active region; wherein the shallow trench has an exposed partial active region on both sides, and the surface of the partial active region is adjacent to the sidewall of the shallow trench to form an initial top corner region; forming an oxidation consumption compensation part on the sidewall of the shallow trench; the oxidation rate of the oxidation consumption compensation part is higher than the oxidation rate of the substrate; and performing an oxidation process on the partial active region and the oxidation consumption compensation part to form a target top corner region, wherein the target top corner region has a rounded corner morphology compared with the initial top corner region. In this way, the active region size reduction after the top corner rounding of the shallow trench can be inhibited.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor process technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] Currently, in the manufacturing process of some semiconductor devices, such as medium-voltage or high-voltage semiconductor devices, it is necessary to round the corners formed by the sidewalls of STI (shallow trench isolation) and the active regions on both sides to alleviate electric field concentration and improve the reliability of the device under relatively high operating voltage.

[0003] In related technologies, the process of rounding the apex is usually achieved by using an oxidation process to optimize the apex shape, making the connection between the STI and the active regions on both sides smoother and forming a rounded morphology. However, at the same time, due to oxidation consumption, the size of the active regions on both sides of the STI is also reduced. Summary of the Invention

[0004] In view of this, several embodiments of this application aim to provide a semiconductor structure and a method for fabricating the same, which can suppress the shrinkage of the active region size after corner rounding.

[0005] One embodiment of this application provides a method for fabricating a semiconductor structure. The method includes: providing a substrate; the substrate including a substrate, the substrate forming a shallow trench defining active regions; wherein, the shallow trench has exposed partial active regions on both sides, and the surface of the partial active regions is adjacent to the sidewall of the shallow trench to form an initial apex region; forming an oxidation consumption compensation portion on the sidewall of the shallow trench; the oxidation rate of the oxidation consumption compensation portion is higher than the oxidation rate of the substrate; performing an oxidation process on the partial active regions and the oxidation consumption compensation portion to form a target apex region, the target apex region having a rounded corner shape compared to the initial apex region; wherein, the oxidation consumption compensation portion is used to pre-compensate for the oxidation consumption of the substrate material in the partial active regions in a first direction before performing the oxidation process; the first direction is the arrangement direction of adjacent active regions located on both sides of the shallow trench.

[0006] Optionally, the substrate is made of silicon; the oxidation consumption compensation part is made of polycrystalline silicon.

[0007] Optionally, the step of forming an oxidation consumption compensation portion on the sidewall of the shallow trench includes: depositing polysilicon on the substrate; using a self-aligned etching process to remove a portion of the polysilicon covering the surface of the partial active region and the bottom wall of the shallow trench, forming a polysilicon sidewall as the oxidation consumption compensation portion; wherein the polysilicon sidewall has an end away from the bottom wall of the shallow trench; along the recess direction of the shallow trench on the substrate surface, the thickness of the end gradually increases in the first direction.

[0008] Optionally, the substrate further includes a pad oxide layer and a hard mask layer stacked on the substrate and located on both sides of the partial active region; the step of providing the substrate includes: providing a semiconductor intermediate structure; the semiconductor intermediate structure includes a semiconductor substrate, the semiconductor substrate having an initial shallow trench formed thereon; an initial pad oxide layer and an initial hard mask layer stacked thereon are formed on the semiconductor substrate surfaces on both sides of the initial shallow trench; and removing a portion of the initial pad oxide layer and a portion of the initial hard mask layer located on the surface of the partial active region by hard mask back etching to obtain the substrate.

[0009] Optionally, based on the characteristics of the shallow trench etching process, the sidewalls of the initial shallow trench are inclined relative to a second direction perpendicular to the surface of the semiconductor substrate; wherein, the semiconductor substrate has inclined portions on both sides of the initial shallow trench that protrude from the initial pad oxide layer and the initial hard mask layer in a first direction; the thickness of the inclined portions in the first direction gradually increases from the substrate surface to the bottom of the initial shallow trench; the step of providing the substrate before performing hard mask back etching further includes: changing the inclined portions to the same material as the hard mask layer; wherein, in the step of removing a portion of the initial pad oxide layer and the initial hard mask layer located on the surface of the partial active region by hard mask back etching, the inclined portions are also removed to reduce the degree of inclination of the sidewalls of the shallow trench relative to the second direction in the resulting substrate.

[0010] Optionally, the initial hard mask layer is made of silicon nitride; the step of changing the tilted portion to the same material as the hard mask layer includes: using an ion implantation process to implant nitrogen atoms into the tilted portion to change the tilted portion to silicon nitride material.

[0011] Optionally, prior to the step of forming an oxidation consumption compensation portion on the sidewall of the shallow trench, the fabrication method further includes: forming an oxidation consumption suppression portion located on the surface of the partial active region; the oxidation rate of the oxidation consumption suppression portion is lower than the oxidation rate of the substrate; wherein the oxidation consumption suppression portion is used to reduce the oxidation consumption of the partial active region in a first direction during the oxidation process.

[0012] Optionally, the substrate further includes a pad oxide layer and a hard mask layer stacked on the substrate and located on both sides of the partial active region; wherein the hard mask layer is made of silicon nitride; the step of forming an oxidation consumption suppression portion on the surface of the partial active region includes: depositing silicon nitride on the substrate; using a self-aligned etching process to remove a portion of the silicon nitride covering the surface of the partial active region and the bottom wall of the shallow trench, forming a first sidewall located on the side of the pad oxide layer and the hard mask layer and a second sidewall located on the sidewall of the shallow trench, respectively; using the first sidewall and the second sidewall for self-alignment, etching the exposed substrate to form a groove on the surface of the partial active region; forming the oxidation consumption suppression portion in the groove, and removing the first sidewall and the second sidewall.

[0013] Optionally, the thickness of the first sidewall and the second sidewall in the first direction is the same as the thickness of the oxidation consumption compensation portion in the first direction, so that the substrate material of the partial active region is not exposed in the oxidation process.

[0014] One embodiment of this application provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described above.

[0015] The unexpected effect of the various embodiments provided in this application is that by forming an oxidation consumption compensation section on the sidewall of the shallow trench, the oxidation consumption of the substrate material in the lateral direction of the active region adjacent to the shallow trench can be compensated before the oxidation process, so that the oxidation consumption of the substrate material on the surface of the active region is reduced in the lateral direction after the corner rounding is performed by the oxidation process. Furthermore, since the oxidation rate of the oxidation consumption compensation section is higher than the oxidation rate of the substrate, the corner rounding effect is achieved faster by the oxidation process, thereby reducing the oxidation consumption of the substrate material on the surface of the active region in the lateral direction and suppressing the shrinkage of the active region size caused by the corner rounding. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a simulated structure after the vertex corners are rounded in related technologies.

[0017] Figure 2 and Figure 3 In response to Figure 1 A schematic diagram of the TCAD simulation analysis results of the simulated structure for the turn-off current.

[0018] Figure 4a and Figure 4b This is a schematic diagram comparing the simulation analysis results of current density and potential distribution under different vertex rounding effects in related technologies.

[0019] Figure 5a and Figure 5bThis is a schematic diagram comparing the simulation analysis results of electric field and potential distribution under different vertex rounding effects in related technologies.

[0020] Figure 6 This is a schematic diagram of data analysis for silicon slice structures.

[0021] Figure 7 This is a schematic diagram of the slice structure of pull-up transistors and pull-down transistors after the vertex corners are rounded in related technologies.

[0022] Figure 8 This is a schematic diagram of the simulation results showing the relationship between the active region size and the threshold voltage in related technologies.

[0023] Figure 9 This is a schematic diagram of the diffusion effect of B ions in related technologies.

[0024] Figure 10 This is a schematic diagram of the initial oxide layer of the growth pad in the method for preparing the semiconductor structure provided in the embodiments of this application.

[0025] Figure 11 This is a schematic diagram of the formation of a hard mask layer and a patterned photoresist layer in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0026] Figure 12 This is a schematic diagram of the semiconductor intermediate structure formed in a method for preparing a semiconductor structure according to an embodiment of this application.

[0027] Figure 13 This is a schematic diagram of nitrogen atom implantation into an inclined portion in a method for fabricating a semiconductor structure according to an embodiment of this application.

[0028] Figure 14 This is a schematic diagram of hard mask back etching in a semiconductor structure fabrication method provided in one embodiment of this application.

[0029] Figure 15 This is a schematic diagram of the deposition of polycrystalline silicon on a substrate in a method for fabricating a semiconductor structure according to an embodiment of this application.

[0030] Figure 16 This is a schematic diagram of the formation of an oxidation consumption compensation part in a method for fabricating a semiconductor structure according to an embodiment of this application.

[0031] Figure 17 This is a schematic diagram of an oxidation process performed to form a target apex region in a semiconductor structure fabrication method provided in one embodiment of this application.

[0032] Figure 18 and Figure 19This is a schematic diagram of STI filling to form a shallow trench isolation structure in a semiconductor structure fabrication method provided in one embodiment of this application.

[0033] Figure 20 and Figure 21 This is a schematic diagram illustrating the formation of N-type and P-type well regions in a semiconductor structure fabrication method provided in one embodiment of this application.

[0034] Figure 22 This is a schematic diagram of the deposition of silicon nitride on a substrate in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0035] Figure 23 This is a schematic diagram of the formation of a first sidewall and a second sidewall in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0036] Figure 24 This is a schematic diagram of forming a groove in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0037] Figure 25 This is a schematic diagram of the formation of an oxidation consumption suppression part in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0038] Figure 26 This is a schematic diagram of the removal of the first and second sidewalls in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0039] Figure 27 This is a schematic diagram of the formation of an oxidation consumption compensation part in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0040] Figure 28 This is a schematic diagram illustrating the oxidation process performed to achieve corner rounding in a semiconductor structure fabrication method provided in another embodiment of this application.

[0041] Explanation of reference numerals in the attached figures:

[0042] 100. Substrate; 101. Substrate; 102. Shallow trench; 103. Partial active region; 110. Initial apex region; 120. Oxidation loss compensation section; 130. Target apex region; 140. Polysilicon layer; 121. End; 150. Pad oxide layer; 160. Hard mask layer; 170. Pad oxide layer; 180. Shallow trench isolation structure; 200. Semiconductor intermediate structure; 210. Semiconductor substrate; 211. Pad 212. Initial oxide layer; 213. Initial hard mask layer; 220. Initial shallow trench; 230. Initial pad oxide layer; 240. Initial hard mask layer; 250. Inclined portion; 310. Oxidation consumption suppression portion; 320. Silicon nitride layer; 330. First sidewall; 340. Second sidewall; 350. Groove; 410. N-type well region; 420. P-type well region; aa. First direction; bb. Second direction. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0044] In this application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0045] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in embodiments of this application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0046] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0047] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. In other words, they should not be construed as limitations on this application.

[0048] In the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "linking," "fixing," "setting," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0049] In some semiconductor devices, the active region forms a apex region adjacent to the STI. This region is formed by the intersection of the active region parallel to the wafer surface and the STI sidewall, i.e., the side of the active region. The shape is relatively sharp. Therefore, in practical applications, electric field concentration is likely to occur in this region, which affects the reliability of the semiconductor device.

[0050] To mitigate electric field concentration in the apex region, during semiconductor device manufacturing, the sharp corners formed by the sidewalls of the STI and the adjacent active regions on both sides are typically rounded to make them smoother and improve reliability. However, in practical applications, different rounding effects—that is, varying degrees of smoothness at the junction of the STI's sidewalls and the active regions on both sides—can also affect the electrical performance of the semiconductor device.

[0051] For example, refer to Figures 1 to 9 ,against Figure 1 The simulation results of the turn-off current Ioff of the simulated structure with rounded apex corners shown are as follows: Figure 2 and Figure 3 As shown in the figure, it can be seen that the current density at the connection between the sidewall of the STI and the active regions on both sides is greater than the current density at the center of the active region.

[0052] The simulation analysis results under different vertex rounding effects can be compared as follows: Figure 4a , Figure 4b and Figure 5a , Figure 5b As shown, in which, Figure 4a , Figure 4b For the comparison of current density and potential distribution, Figure 5a , Figure 5b This is a comparison of the electric field and potential distribution. It can be seen that... Figure 4a and Figure 5a The sidewalls of the STI and the connection between them and the active regions on both sides are compared to Figure 4b and Figure 5b More tactful, in contrast, Figure 4b and Figure 5b The potential lines are denser, and the current density and electric field strength are greater. According to data analysis by technicians, Figure 4a and Figure 5a medium structure relative to Figure 4b and Figure 5b In the structure described, the turn-off current Ioff is reduced by approximately half, the saturation drain current Idsat is reduced by approximately 4%, and the threshold voltage parameters Vtgm and Vtlin are reduced by approximately 20mV. Specifically, refer to Table 1 for the TCAD simulation data of various performance parameters of the semiconductor device under different corner rounding effects. Here, Rounding represents the tangent circle radius of the arc surface formed at the junction of the STI sidewall and the active region surface after corner rounding. This can be determined by... Figure 6 The slice results shown are obtained through data analysis. It can be understood that the larger the value, the higher the smoothness. Vtgm represents the threshold voltage under the maximum transconductance method in the linear region, Vtlin represents the threshold voltage in the linear region, Idlin represents the drain current in the linear region, Vtsat represents the threshold voltage in the saturation region, Idsat represents the drain current in the saturation region, and Ioff represents the turn-off current.

[0053] Table 1

[0054]

[0055] As can be seen from the data in Table 1, the electrical performance of the semiconductor structure will vary depending on the smoothness of the connection between the sidewall and the active region surface of the STI.

[0056] Therefore, the required corner rounding effect during manufacturing varies depending on the type of semiconductor device or its performance requirements. Since corner rounding requires an oxidation process, pursuing a better rounding effect results in more substrate material being oxidized and consumed laterally by the active regions adjacent to the STI (Surface Mount Technology), thus compressing the size of the active regions. For example, see reference... Figure 7For pull-down transistors (PD) and pull-up transistors (PU) in SRAM, PD requires a higher degree of smoothness to achieve lower turn-off current. However, if the active region size (CD) itself is relatively small, for example... Figure 7 In medium-density polyurethane (PU), excessive oxidation consumption can lead to an excessively small active region density (CD), thus impacting performance. For example... Figure 8 As shown, as the active region CD shrinks, the threshold voltage decreases significantly when it shrinks to a certain extent. Research has found that, as... Figure 9 As shown, the significant drop in threshold voltage is actually due to the shrinkage of the active region CD and the diffusion effect of B ions injected into the P-well.

[0057] Therefore, there is an urgent need for a semiconductor structure fabrication method that can achieve good corner rounding while suppressing the shrinkage of the active region size due to oxidation.

[0058] Please see Figures 10 to 21 One embodiment of this application provides a method for fabricating a semiconductor structure. The semiconductor structure can be applied in medium-voltage (MV) or high-voltage (HV) devices, such as semiconductor devices operating at voltages above 20V. In some embodiments, it can also be applied in low-voltage semiconductor devices. The method for fabricating the semiconductor structure may include the following steps.

[0059] S110: Provides semiconductor intermediate structure.

[0060] In this embodiment, as Figure 12 As shown, the semiconductor intermediate structure 200 includes a semiconductor substrate 210, on which an initial shallow trench 220 is formed. The initial shallow trench 220 extends from the surface of the semiconductor substrate 210 to its bottom. Specifically, the shallow trench 102 formed on the semiconductor substrate 210 can be formed using an STI etching process.

[0061] In this embodiment, the semiconductor substrate 210 can serve as the basic structure of a semiconductor device, not only providing mechanical support but also influencing the device's electrical performance, such as threshold voltage and carrier mobility, through doping with ions. Specifically, the semiconductor substrate 210 can be made of silicon (Si) or, depending on requirements, of other semiconductor materials, such as gallium nitride (GaN).

[0062] In this embodiment, a stacked initial pad oxide layer 230 and an initial hard mask layer 240 are formed on the surface of the semiconductor substrate 210 on both sides of the initial shallow trench 220. The initial pad oxide layer 230 and the initial hard mask layer 240 can be patterned structures formed by etching during the STI etching process, and can also serve as masks in subsequent process steps. Specifically, the initial pad oxide layer 230 is located between the initial hard mask layer 240 and the semiconductor substrate 210. The initial pad oxide layer 230 can serve as a masking layer in the subsequent ion implantation process to prevent damage to the surface of the semiconductor substrate 210 during ion implantation.

[0063] refer to Figure 10 For example, in some embodiments, such as Figure 10 As shown, a pad oxide layer 211, with a thickness of 55 Å, is first grown on the semiconductor substrate 213 using a furnace tube process. Then, ions are implanted into the semiconductor substrate 213 to form a deep well region, such as implanting N-type ions to form a DNW (Deep N-Well). Next, as... Figure 11 As shown, a hard mask material, such as SiN, is deposited on the initial oxide layer 211 to form a hard mask layer initial 212. A patterned photoresist layer for photolithography is then formed on the hard mask layer initial 212, defining the etching locations for STI. Finally, as... Figure 12 As shown, STI etching yields the semiconductor intermediate structure 200. The initial shallow trench 220 can be used to isolate the active regions located on either side of it. In some embodiments, NMOS and PMOS can be formed on the active regions on either side of the initial shallow trench 220 in subsequent processes. STI can be formed by filling the initial shallow trench 220 with oxide, achieving insulation and isolation of the active regions on both sides.

[0064] In this embodiment, based on the characteristics of shallow trench etching, such as when dry etching is used, the opening width of the initial shallow trench 220 gradually decreases along its concave direction. This results in the sidewalls of the initial shallow trench 220 not being ideally perpendicular to the surface of the semiconductor substrate 210, but rather inclined relative to the vertical direction of the semiconductor substrate 210 surface. The semiconductor substrate 210 has inclined portions 250 on both sides of the initial shallow trench 220, protruding from the initial pad oxide layer 230 and the initial hard mask layer 240 in a first direction aa. The first direction aa can be the arrangement direction of adjacent active regions located on both sides of the initial shallow trench 220, as referenced. Figure 12 This can also be understood as the direction in which one sidewall of the initial shallow trench 220 faces the other sidewall. In this embodiment, the vertical direction of the semiconductor substrate 210 surface can be the second direction bb.

[0065] like Figure 12As shown, the inclined portion 250 may be the portion of the semiconductor substrate 210 that is extra compared to the semiconductor substrate 210 after the shallow trench 102 is etched in an ideal state. It can be understood that, relative to the opening width of the initial shallow trench 220 along its concave direction, the thickness of the inclined portion 250 in the first direction aa gradually increases from the surface of the substrate 101 toward the bottom of the initial shallow trench 220.

[0066] S120: Change the inclined section to the same material as the hard mask layer.

[0067] In this embodiment, an oxidation consumption compensation portion needs to be formed on the sidewall of the initial shallow trench 220. If the semiconductor substrate 210 has a tilted portion 250, it is difficult to form a regular oxidation consumption compensation portion on the sidewall of the initial shallow trench 220, which affects the final corner rounding effect achieved by the oxidation process. Therefore, in this embodiment, the tilted portion 250 needs to be modified to facilitate its removal in subsequent processes and avoid affecting the corner rounding effect. However, it should be noted that the step of removing the tilted portion 250 is not necessary for achieving the technical effect of suppressing the shrinkage of the active region in this application. It only facilitates the formation of a regular oxidation consumption compensation portion, which simplifies the process while ensuring the corner rounding effect. In some embodiments, other process steps can also be used to form a regular oxidation consumption compensation portion.

[0068] In this embodiment, as Figure 13 As shown, nitrogen atoms can be implanted into the tilted portion 250 using an ion implantation process to change the tilted portion 250 to silicon nitride. Thus, if the initial hard mask layer 240 is also made of silicon nitride, the tilted portion 250 can be removed during the subsequent hard mask etch-back process on the initial hard mask layer 240, eliminating the need for an additional step to remove the tilted portion 250 and simplifying the process. In some embodiments, changing the tilted portion 250 to silicon nitride can also be achieved using a decoupled plasma nitride deposition process, using N2 as the ion source.

[0069] S130: By etching back through a hard mask, a portion of the initial pad oxide layer and a portion of the initial hard mask layer located on the surface of a portion of the active region are removed to obtain the substrate. The inclined portion is also removed to reduce the inclination of the sidewalls of the shallow trenches relative to the second direction in the resulting substrate.

[0070] In this embodiment, the surface of the active region 103 covered by part of the initial pad oxide layer 230 and part of the initial hard mask layer 240 is exposed by hard mask pull back. On the one hand, this makes it easier for the subsequent oxidation process to act on the active region 103 and achieve corner rounding. On the other hand, it can also reduce the difficulty of STI filling in the subsequent process, improve the filling quality of STI, and make it less likely to produce voids.

[0071] In this embodiment, as Figure 14 As shown, when the initial hard mask layer 240 is made of silicon nitride, a wet process can be used for SiN pull-back. For example, the initial layer can be soaked in phosphoric acid at 160°C for 50 seconds, followed by soaking in APM at 45°C for 300 seconds. It should be noted that the soaking temperature and time during SiN pull-back can be determined based on the required thickness of the initial pad oxide layer 230 and the initial hard mask layer 240 to be pushed back in the first direction aa. It is necessary to ensure that the tilted portion 250 is completely removed before reaching the required thickness.

[0072] In this embodiment, as Figure 14 As shown, the substrate 100 may include a substrate 101, on which a shallow trench 102 is formed, defining an active region. The shallow trench 102 has exposed portions of active regions 103 on both sides, and the surface of the portions of active regions 103 is adjacent to the sidewalls of the shallow trench 102 to form an initial apex region 110. A pad oxide layer 150 and a hard mask layer 160 are covered on the surfaces of the substrate 101 on both sides of the portions of active regions 103; that is, the remaining initial pad oxide layer 230 and the remaining initial hard mask layer 240 after hard mask back etching.

[0073] In this embodiment, as Figure 14 As shown, the initial apex region 110 has a sharp-angled shape, which is prone to electric field concentration in the working environment, thus affecting the reliability of the semiconductor structure.

[0074] In this embodiment, the shallow trench 102 can be used to fill the isolation material, such as oxide, in subsequent processes to achieve isolation between adjacent active regions.

[0075] S140: Deposit polycrystalline silicon on a substrate.

[0076] Specifically, such as Figure 15 As shown, polysilicon is deposited on substrate 100 using a furnace tube process to form a polysilicon layer 140 covering the entire substrate 100, wherein the thickness of the polysilicon layer 140 can be controlled within the range of 40 Å to 50 Å.

[0077] In this embodiment, the deposited polysilicon can be used to form the oxidation loss compensation section. Of course, in some possible embodiments, if the oxidation loss compensation section is made of other materials, then the corresponding other materials are deposited for subsequent formation of the oxidation loss compensation section.

[0078] S150: Using a self-aligned etching process, a portion of the polysilicon covering part of the active area surface and the bottom wall of the shallow trench is removed, and the resulting polysilicon sidewall serves as an oxidation consumption compensation section.

[0079] In this embodiment, reference Figure 15 and Figure 16 Self-alignment is performed using polysilicon in the second direction to remove polysilicon extending along the first direction aa on the substrate 100. This includes a first portion of polysilicon covering a portion of the surface of the active region 103 and the bottom wall of the shallow trench 102, and a second portion of polysilicon covering the hard mask layer 160, forming a polysilicon sidewall extending along the second direction on the sidewall of the shallow trench 102 as an oxidation consumption compensation section 120. Specifically, dry etching can be used, and EPD (Endpoint Detection) technology can be used to stop on the hard mask layer 160 to complete the etching.

[0080] In addition to the polysilicon sidewalls located on the sidewalls of the shallow trench 102, a third portion of polysilicon extending along the second direction is also formed on the sides of the pad oxide layer 150 and the hard mask layer 160. This third portion of polysilicon can be oxidized together in a subsequent oxidation process.

[0081] In this embodiment, since the self-aligned etching process uses the polysilicon in the second direction as the self-alignment reference to etch the polysilicon extending in the first direction aa, a certain degree of etching will also occur in the polysilicon in the second direction during the etching process, and as... Figure 15 and Figure 16 As shown, based on the characteristics of the self-aligned etching process, the polysilicon sidewall formed has an end 121 on the side away from the bottom wall of the shallow trench 102, wherein the thickness of the end 121 gradually increases in the first direction aa along the recess direction of the shallow trench 102 on the surface of the substrate 101.

[0082] In this embodiment, the deposited polysilicon is self-aligned to form a polysilicon sidewall serving as an oxidation consumption compensation part 120. This eliminates the need for a photomask, saving process costs. Furthermore, the presence of the end 121 in the formed polysilicon sidewall allows for a smoother target corner region after subsequent oxidation processes, resulting in a better rounding effect.

[0083] S160: An oxidation process is performed on a portion of the active region and the oxidation consumption compensation section to form the target apex region.

[0084] In this embodiment, an oxidation process is performed on a portion of the active region 103 and the oxidation consumption compensation unit 120, specifically as follows: Figure 17 As shown, oxidation is performed using ROX (Rapid Oxidation) technology or a thermal processing platform based on RTP (Rapid Thermal Processing). Through the oxidation process, the accelerated oxidation by the oxidation consumption compensation unit 120 can smooth the originally sharp initial apex region 110 with the generated silicon dioxide, forming a target apex region 130 with a rounded morphology compared to the initial apex region 110, thereby achieving a corner rounding effect.

[0085] In this embodiment, as described above, the oxidation consumption compensation unit 120 has an end portion 121 formed due to process characteristics. The end portion 121 is located at the connection between the part of the active region 103 and the oxidation consumption compensation unit 120. The end portion 121 has a smaller thickness than other positions, which makes the oxidation rate of the end portion 121 faster in the oxidation process. As a result, the final target apex region 130 will have a better rounding effect, that is, it will be smoother.

[0086] In this embodiment, the oxidation rate of the oxidation consumption compensation unit 120 can be higher than the oxidation rate of the substrate 101. For example, the oxidation consumption compensation unit 120 is made of polycrystalline silicon and the substrate 101 is made of silicon. The oxidation rate of polycrystalline silicon when it is oxidized is higher than that of silicon.

[0087] Specifically, the oxidation process can be controlled to oxidize the entire oxidation consumption compensation section 120 to SiO2, and to oxidize a certain thickness of SiO2, such as 10 Å to 20 Å, on the surface of a portion of the active region 103. The thickness of the SiO2 formed on the surface of the portion of the active region 103 in the second direction is less than the thickness of the SiO2 formed in the oxidation consumption compensation section 120 in the first direction aa.

[0088] In this embodiment, the oxidation consumption compensation unit 120 can be used to pre-compensate for the oxidation consumption of substrate material in the first direction aa of a portion of the active region 103 before performing the oxidation process. Specifically, by providing the oxidation consumption compensation unit 120, the substrate material consumed in the first direction aa during the oxidation process can be offset, thereby reducing the size loss of a portion of the active region 103. That is, it can be understood as increasing the size of the active region in the first direction aa in advance, so that the size loss of the active region in the first direction aa caused by oxidation consumption after the oxidation process is naturally reduced or even avoided.

[0089] In this embodiment, the oxidation rate of the oxidation loss compensation section 120 is higher than that of the substrate 101, making the configuration of the oxidation loss compensation section 120 more flexible. Specifically, for example, when it is necessary to ensure that the oxidation loss compensation section 120 is completely oxidized and that a certain thickness of oxidation is achieved on the surface of a portion of the active region 103, the oxidation rate of the oxidation loss compensation section 120 is higher than that of the substrate 101, allowing the oxidation loss compensation section 120 to be made thicker. This means that more compensation can be made for the dimensional loss of the portion of the active region 103 in the first direction aa, resulting in a smaller reduction in the size of the portion of the active region 103. At the same time, based on the characteristic that the oxidation rate of the oxidation loss compensation section 120 is higher than that of the substrate 101, the corner rounding speed can be achieved faster, resulting in higher process efficiency and easier control.

[0090] In this embodiment, the silicon dioxide formed by the oxidation process can be used as the pad oxide layer 170 (Liner OX), which, in addition to achieving corner rounding, can also passivate etching damage and optimize interface quality to improve the oxide filling quality of subsequent STI.

[0091] S170: STI filling is performed on the liner oxide layer formed by the oxidation process to form a shallow trench isolation structure.

[0092] In this embodiment, as Figure 18 As shown, TEOS is deposited for the opening formed in the pad oxide layer 170 as an isolation material. It can then be annealed at a specific temperature to make the deposited TEOS more dense, eliminating internal stress and enhancing interfacial bonding with the pad oxide layer 170. It can then be smoothed using a TEOS CMP process, where a hard mask layer 160 can be used as a stop layer, and EPD technology is used to stop the process on the hard mask layer 160.

[0093] Furthermore, the remaining hard mask layer 160 can be removed using a combined process of phosphoric acid and DHF (diluted hydrofluoric acid) to form a layer such as... Figure 19 The shallow trench isolation structure 180 shown is located between adjacent active regions.

[0094] S180: Different types of ion implantation are performed on the active regions located on both sides of the shallow trench isolation structure to form P-type and N-type well regions respectively.

[0095] In this embodiment, as Figure 20As shown, the N-type well region 410 can be fabricated first. After the active region on one side of the shallow trench isolation structure 180 to be implanted with ions is exposed and developed using photolithography, the ion implantation process is performed. Specifically, N-type ions such as phosphorus ions and arsenic ions can be selected, and the implantation can be performed in three stages, each time implanted to a different depth in the substrate, ultimately forming the N-type well region 410.

[0096] Similarly, such as Figure 21 As shown, the photoresist set during the fabrication of the N-type well region 410 is removed first, and then the P-type well region 420 is fabricated. Similarly, the active region on the other side of the shallow trench isolation structure 180 can be exposed and developed using photolithography, followed by ion implantation. Specifically, P-type ions such as B⁺ or BF₂⁺ can be selected. Since boron ions are relatively light, they can be implanted in four stages, each time to a different depth in the substrate, ultimately forming the P-type well region 420.

[0097] In this embodiment, after the N-type well region 410 and the P-type well region 420 are fabricated, the basic substrate unit of NMOS and PMOS is formed, including the N-type well region 410 and the P-type well region 420, and the shallow trench isolation structure 180 located between the N-type well region 410 and the P-type well region 420.

[0098] In this embodiment, an unexpected effect is that by forming an oxidation consumption compensation portion 120 on the sidewall of the shallow trench 102, the oxidation consumption of the substrate material of the active region 103 adjacent to the shallow trench 102 in the first direction aa can be compensated before the oxidation process. This reduces the oxidation consumption of the substrate material on the surface of the active region 103 in the first direction aa after the corner rounding is performed by the oxidation process. Furthermore, since the oxidation rate of the oxidation consumption compensation portion 120 is higher than the oxidation rate of the substrate 101, the corner rounding effect is achieved faster by the oxidation process, thereby reducing the oxidation consumption of the substrate material on the surface of the active region 103 in the first direction aa and suppressing the problem of active region size reduction caused by corner rounding.

[0099] Please see Figures 22 to 28 And at the same time refer to Figures 1 to 21 Another embodiment of this application provides a method for fabricating a semiconductor structure. The difference between this embodiment and the foregoing embodiments is that, after completing step S130, the method for fabricating the semiconductor structure includes the following steps.

[0100] S140': Deposit silicon nitride on a substrate.

[0101] Specifically, such as Figure 22As shown, silicon nitride is deposited on substrate 100 using a CVD (chemical vapor deposition) process to form a silicon nitride layer 320 covering the entire substrate 100.

[0102] In this embodiment, the silicon nitride layer 320 formed can be used for self-alignment during the subsequent formation of the oxidation consumption suppression section 310. After the oxidation consumption suppression section 310 is formed, if the hard mask layer 160 is also made of silicon nitride, the remaining silicon nitride layer 320 can be removed at the same time as the hard mask layer 160 is removed, which can save process steps.

[0103] S150': Using a self-aligned etching process, a portion of the silicon nitride covering part of the active area surface and the bottom wall of the shallow trench is removed to form a first sidewall located on the side of the pad oxide layer and the hard mask layer, and a second sidewall located on the sidewall of the shallow trench.

[0104] In this embodiment, reference Figure 22 and Figure 23 Similar to S150 in the aforementioned embodiment, self-alignment is performed using silicon nitride in the second direction to remove silicon nitride extending along the first direction aa on the substrate 100. This includes a first portion of silicon nitride covering a portion of the surface of the active region 103 and the bottom wall of the shallow trench 102, and a second portion of silicon nitride covering the hard mask layer 160. The remaining silicon nitride forms a first sidewall 330 and a second sidewall 340. The first sidewall 330 is located on the sides of the pad oxide layer 150 and the hard mask layer 160, and the second sidewall 340 is located on the sidewall of the shallow trench 102. Specifically, dry etching can be used, and EPD (Endpoint Detection) technology can be used to stop the etching on the hard mask layer 160 to complete the etching.

[0105] S160': Self-alignment is performed using the first and second sidewalls to etch the exposed substrate to form a groove on a portion of the active region surface.

[0106] In this embodiment, as Figure 24 As shown, a self-aligned process can be further utilized, using the first sidewall 330 and the second sidewall 340 as masks, to etch the exposed substrate between the first sidewall 330 and the second sidewall 340 to form a groove 350 located in a portion of the active region 103. In this embodiment, the substrate exposed on the bottom wall of the shallow trench 102 is also etched to form the groove 350. Of course, in some embodiments, a mask can also be provided on the bottom wall of the shallow trench 102 to prevent it from being etched.

[0107] In this embodiment, steps S150' and S160' can be completed without the need for an additional photomask, thus saving process costs.

[0108] S170': The oxidation consumption inhibition section is formed in the groove, and the first sidewall and the second sidewall are removed.

[0109] In this embodiment, by forming an oxidation consumption suppression portion 310 embedded in the substrate within the groove 350, the portion of the substrate that was originally etched away can be replaced as a component constituting the partial active region 103. Specifically, the oxidation consumption suppression portion 310 can be located at the surface of the partial active region 103, so that the substrate material covered by it will not be oxidized and consumed during the oxidation process. Since the oxidation rate of the oxidation consumption suppression portion 310 is lower than the oxidation rate of the substrate, when the oxidation process achieves the effect of rounding the apex corner, the oxidation consumption of the oxidation consumption suppression portion 310 itself is less. Therefore, the oxidation consumption of the partial active region 103 in the first direction aa can be reduced, thereby effectively reducing the size loss of the partial active region 103 in the oxidation process.

[0110] In this embodiment, the oxidation consumption suppression section 310 can be made of SiC. Specifically, such as... Figure 25 and Figure 26 As shown, SiC can be formed on the substrate surface within the groove 350 as an oxidation consumption suppression part 310 using EPI epitaxial technology, and the first sidewall 330 and the second sidewall 340 can be removed to facilitate subsequent oxidation processes.

[0111] Subsequent steps can be the same as S140 to S180 in the aforementioned embodiments. For example, refer to... Figure 27 A 40 Å to 50 Å polycrystalline silicon layer 140 can be deposited using a furnace tube process. Then, a portion of the polycrystalline silicon extending along the first direction aa is removed, forming a polycrystalline silicon sidewall that serves as an oxidation loss compensation section 120. The corners are then rounded using an oxidation process to form a layer resembling... Figure 28 The target apex region 130 is shown in the diagram. Subsequently, it can be filled with STI and implanted with ions to ultimately form the basic substrate cells for NMOS and PMOS.

[0112] In this embodiment, an unexpected effect is that using SiC as a component of part of the active region 103 on the surface of the substrate 101 near the shallow trench 102 can have the following advantages.

[0113] First, as shown in Table 2, the oxidation rate of SiC is much lower than that of polycrystalline silicon and monocrystalline silicon. This means that during the oxidation process, the oxidation rate at which the oxidation consumption suppression section 310 is oxidized to silicon dioxide is slower compared to the oxidation consumption compensation section 120 and the substrate. Therefore, while ensuring the corner rounding effect of the oxidation process, the oxidation consumption of some active regions 103 can be reduced. (Reference) Figure 28As can be seen, when the oxidation consumption compensation part 120 is completely oxidized to silicon dioxide through the oxidation process and the corner rounding effect is achieved, the embedded SiC is only oxidized to a thin layer of silicon dioxide on the surface, thus suppressing part of the size loss of the active region 103.

[0114] Table 2

[0115]

[0116] Secondly, as mentioned earlier, the purpose of rounding the apex corners in this application is to reduce electric field concentration and prevent tip discharge, which could affect reliability. In this embodiment, by replacing part of the substrate material of the active region 103 with SiC, relying on the wide bandgap characteristics of SiC and optimized device technology, the electric field concentration factor (maximum electric field / average electric field) can be reduced from 2.5-3.5 for silicon devices to 1.8-2.2. This significantly improves the reliability of devices in high-power applications under medium and high voltage operating environments.

[0117] Specifically, according to research by technical personnel, firstly, SiC possesses a high critical breakdown electric field strength. The critical breakdown electric field strength of SiC can reach 2.0-4.0 MV / cm, while that of silicon is only 0.3 MV / cm, allowing devices to withstand the same voltage with thinner epitaxial layers. For example, with a working voltage of 1200V, silicon devices typically require an epitaxial layer with a thickness of 100μm, while SiC devices only require an epitaxial layer with a thickness of 10-15μm. Secondly, SiC has a higher carrier saturation drift velocity, which can reduce the carrier accumulation probability in high electric field regions. For example, the electron saturation velocity of SiC reaches 2 × 10⁻⁶. 7 cm / s, while silicon is 1×10 7 cm / s. Thirdly, by using the SiN pull-back process platform to embed SiC, not only are the process steps simplified, but the embedded SiC can also replace the original silicon substrate, reducing the surface electric field by 40-60% and achieving lateral field modulation. The embedded SiC can achieve a charge balance capability that is 5-8 times higher than that of silicon, which can improve the uniformity of the electric field in the target apex region 130 by 30%.

[0118] In some embodiments, the thickness of the first sidewall and the second sidewall in the first direction may be the same as the thickness of the oxidation consumption compensation portion in the first direction, so that the substrate material of a portion of the active region is not exposed in the oxidation process.

[0119] For details, please refer to Figure 26 and Figure 27Since the removal of the first sidewall 330 and the second sidewall 340 exposes the surface of the previously covered active region 103, it is easily oxidized and consumed during the oxidation process, resulting in a reduction in the size of the active region. Therefore, when the oxidation consumption compensation part 120 is subsequently formed, if the thickness of the oxidation consumption compensation part 120 is the same as that of the first sidewall 330 and the second sidewall 340, the oxidation consumption compensation part 120 can be used to re-cover the exposed surface of the active region 103 to avoid oxidation consumption during the oxidation process.

[0120] Another embodiment of this application provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in any of the foregoing embodiments.

[0121] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0122] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0123] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0124] It is understood that in the description of this application, when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it may mean that it is directly above another layer or region, or that it contains other layers or regions between itself and another layer or region. Furthermore, if the component is flipped, the layer or region will be located "below" or "under" another layer or region.

[0125] The above description is merely a specific embodiment of this application, but the protection scope of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided; the substrate includes a base, the base having a shallow trench defining an active region; wherein, the shallow trench has exposed portions of the active region on both sides, and the surfaces of the portions of the active region are adjacent to the sidewalls of the shallow trench to form an initial apex region; An oxidation consumption compensation section is formed on the sidewall of the shallow trench; the oxidation rate of the oxidation consumption compensation section is higher than the oxidation rate of the substrate. An oxidation process is performed on the active region and the oxidation consumption compensation section to form a target apex region, which has a rounded corner shape compared to the initial apex region. The oxidation consumption compensation section is used to pre-compensate for the oxidation consumption of the substrate material in the active region in a first direction before the oxidation process, and the oxidized thickness of the active region in the second direction during the oxidation process is less than the oxidized thickness of the oxidation consumption compensation section in the first direction. The first direction is the arrangement direction of adjacent active regions located on both sides of the shallow trench, and the second direction is perpendicular to the semiconductor substrate surface.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate is made of silicon; the oxidation consumption compensation part is made of polycrystalline silicon.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The step of forming an oxidation loss compensation section on the sidewall of the shallow trench includes: Polycrystalline silicon is deposited on the substrate; Using a self-aligned etching process, a portion of the polysilicon covering the surface of the active region and the bottom wall of the shallow trench is removed, forming a polysilicon sidewall as the oxidation consumption compensation part; wherein, the polysilicon sidewall has an end away from the bottom wall of the shallow trench; along the recess direction of the shallow trench on the substrate surface, the thickness of the end gradually increases in the first direction.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The substrate further includes a pad oxide layer and a hard mask layer stacked on the substrate and located on both sides of the partial active region; the step of providing the substrate includes: A semiconductor intermediate structure is provided; the semiconductor intermediate structure includes a semiconductor substrate, the semiconductor substrate having an initial shallow trench formed thereon; and stacked initial pad oxide layers and initial hard mask layers are formed on the semiconductor substrate surfaces on both sides of the initial shallow trench. By etching back through a hard mask, a portion of the initial pad oxide layer and a portion of the initial hard mask layer located on the surface of the active region are removed to obtain the substrate.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, Based on the characteristics of shallow trench etching process, the sidewalls of the initial shallow trench are inclined relative to the second direction; wherein, the semiconductor substrate has inclined portions on both sides of the initial shallow trench that protrude from the initial pad oxide layer and the initial hard mask layer in the first direction; the thickness of the inclined portions in the first direction gradually increases from the substrate surface to the bottom of the initial shallow trench; The step of providing the substrate before performing hard mask etchback also includes: The inclined portion is changed to the same material as the hard mask layer; In the step of removing a portion of the initial pad oxide layer and the initial hard mask layer located on the surface of the partial active region by hard mask back etching, the inclined portion is also removed to reduce the inclination of the sidewalls of the shallow trench relative to the second direction in the resulting substrate.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The initial hard mask layer is made of silicon nitride; The step of changing the inclined portion to the same material as the hard mask layer includes: Nitrogen atoms are implanted into the tilted portion using an ion implantation process to change the tilted portion into a silicon nitride material.

7. The method for preparing a semiconductor structure according to claim 2, characterized in that, Prior to the step of forming an oxidation consumption compensation section on the sidewall of the shallow trench, the preparation method further includes: An oxidation consumption suppression section is formed on the surface of the active region; the oxidation rate of the oxidation consumption suppression section is lower than the oxidation rate of the substrate; wherein the oxidation consumption suppression section is used to reduce the oxidation consumption of the active region in a first direction during the oxidation process.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The substrate further includes a pad oxide layer and a hard mask layer stacked on the substrate and located on both sides of the partial active region; wherein the hard mask layer is made of silicon nitride. The step of forming an oxidation consumption suppression portion located on the surface in the partially active region includes: Silicon nitride is deposited on the substrate; Using a self-aligned etching process, a portion of silicon nitride covering the surface of the active region and the bottom wall of the shallow trench is removed to form a first sidewall located on the side of the pad oxide layer and the hard mask layer, and a second sidewall located on the sidewall of the shallow trench. Self-alignment is performed using the first and second sidewalls to etch the exposed substrate to form a groove on the surface of the partial active region. The oxidation consumption inhibition section is formed in the groove, and the first sidewall and the second sidewall are removed.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The thickness of the first sidewall and the second sidewall in the first direction is the same as the thickness of the oxidation consumption compensation portion in the first direction, so that the substrate material of the partial active region is not exposed in the oxidation process.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared using the semiconductor structure preparation method described in any one of claims 1 to 9.

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