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Semiconductor storage working at low power consumption

A memory and semiconductor technology, applied in static memory, digital memory information, information storage, etc., can solve problems such as level drop

Inactive Publication Date: 2005-08-03
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Since low-voltage operation is effective in reducing power consumption, the level of the external power supply voltage supplied from the outside tends to decrease.

Method used

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  • Semiconductor storage working at low power consumption
  • Semiconductor storage working at low power consumption
  • Semiconductor storage working at low power consumption

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0109] Referring to FIG. 1 , a semiconductor memory 1000 according to Embodiment 1 of the present invention includes a memory array unit 10 . The memory array unit 10 includes a memory cell array 20 , a row selection unit 30 , a column selection unit, and a sense amplifier 40 .

[0110] The memory cell array 20 has a plurality of memory cells MC arranged in rows and columns. The structure of the memory cell MC is not particularly limited, and various types of DRAM (Dynamic Random Access Memory) cells can be applied to the invention of the present application.

[0111] A word line WL for performing row selection is arranged corresponding to each row of memory cells MC. Bit line pairs BLP are arranged corresponding to each column of memory cells MC. Bit line pair BLP has complementary bit lines BL and / BL. In each memory cell row, each memory cell MC is connected to one of bit lines BL and / BL. FIG. 1 typically shows the arrangement of word line and bit line pairs for one me...

Embodiment 2

[0237] In Embodiment 2, the configuration of the internal power supply circuit for maintaining the control responsiveness of the internal power supply voltage in the same manner corresponding to external power supply voltages of different levels will be described.

[0238] First, the difference in the set level of the internal power supply voltage corresponding to the external power supply voltage level will be described using FIG. 13 .

[0239] Referring to FIG. 13 , in Example 2, two types of external power supply voltages, 2.5V series and higher 2.7V series, are considered.

[0240] When applying 2.7V series external power supply voltage, step down the external power supply voltage Ext.Vdd (2.7V), and set the memory array power supply voltage VDDS and peripheral circuit power supply voltage VDDP to 2.0V and 2.5V respectively. The external power supply voltage Ext.Vdd (2.7V) is boosted to set the word line voltage VPP to 3.7V. In addition, substrate voltage VBB is set to ne...

Embodiment 3

[0330] In the semiconductor memory according to the embodiment of the present invention, a plurality of voltage levels can be applied to the I / O signal level and the external power supply voltage. As a result, the design of semiconductor memories with different applied I / O signal levels and external power supply voltage levels can be made common.

[0331] As already explained, when such a general-purpose design is used, the operation of switching the internal power supply circuit is set in a fixed manner according to operating conditions such as the applied I / O signal level and the level of the external power supply voltage. The level of the control signal for the state. In Embodiment 3, a structure capable of easily detecting applied operating conditions from outside the semiconductor memory will be described.

[0332] Referring to FIG. 23, the test mode control circuit 700 of Embodiment 3 has a test mode entry circuit 702, 704 that responds to a combination of address bits ...

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Abstract

In a low power consumption mode, an internal power supply circuit produces an internal power supply voltage by electrically coupling an internal power supply line to either an external power supply line or a ground line through a transistor. Accordingly, in the low power consumption mode, supply of an operating current to a reference voltage generation circuit, a buffer circuit, an internal power supply voltage generation circuit and a voltage booster circuit is discontinued, allowing for reduction in power consumption of the internal power supply circuit itself.

Description

technical field [0001] The present invention relates to semiconductor memories, and more particularly, to semiconductor memories capable of operating with low power consumption. Background technique [0002] In recent years, semiconductor memories that can be driven with low power consumption have been demanded in order to meet the needs of being mounted on portable devices that are driven by batteries. In order to meet such demands, semiconductor memories are provided with a low power consumption mode. This low power consumption mode is used to set most of the internal circuits to To wait for the working state to reduce power consumption. That is, the power consumption of the semiconductor memory can be reduced by switching between the normal mode and the low power consumption mode according to an external operation request. [0003] Since low-voltage operation is effective in reducing power consumption, the level of the external power supply voltage supplied from the out...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/407G11C5/14G11C29/14H02M3/07
CPCG11C5/147G11C5/14
Inventor 冈本武郎山内忠昭松本淳子
Owner MITSUBISHI ELECTRIC CORP