Gate driving circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded gate driving modules, and the N cascaded gate driving modules are divided into multiple driving areas in physical layout. A pre-charging unit of a first-stage gate driving module of each driving area is connected with at least one pre-charging trigger signal source. The pre-charging unit of a non-first-stage gate driving module of the same driving area is connected with a stage transmission output end of an upper-stage gate driving module. Therefore, the first-stage module of each driving area obtains sufficient pre-charging charges through an independent pre-charging trigger signal source, so as to output a stage transmission signal with good waveform, restore a high-quality stage transmission chain in the area, and effectively improve the problem of insufficient pre-charging of a driving control node caused by the deterioration of the stage transmission signal.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In liquid crystal displays (LCDs) or organic light-emitting diode (OLEDs), the gate driver on array (GOA) circuit achieves line-by-line scanning through step-by-step transmission signals. For long, narrow displays (such as ultrawide or strip-shaped displays), the transmission signals need to be transmitted over long distances step by step. During this transmission process, the waveform of the transmission signals gradually deteriorates due to various factors such as parasitic resistance and capacitance of the traces, transistor aging, and in-plane loads. These factors cause the waveform to become less sharp at the edges and its amplitude to decrease.

[0003] However, the degraded stage-transmitted signal, used as the input trigger signal for the next stage of GOA, leads to insufficient pre-charge of its driving control node (Q point), further degrading the stage-transmitted signal output from that stage. This progressive deterioration eventually causes a decrease in the charging voltage of the far-end pixels, resulting in uneven brightness where the display brightness gradually decreases from the near end to the far end.

[0004] Therefore, how to improve the insufficient Q-point precharge caused by the degradation of the transmission signal is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a gate driving circuit and a display panel. The first-stage module of each driving region of this application obtains sufficient pre-charge charge through an independent pre-charge trigger signal source, thereby outputting a cascade signal with good waveform. A high-quality cascade chain is restored within the region, effectively improving the problem of insufficient pre-charge of the driving control node due to the degradation of the cascade signal.

[0006] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving modules. Each gate driving module includes at least a drive control node, and a pre-charge unit and an output unit connected to the drive control node. The pre-charge unit is used to pre-charge the drive control node, and the output unit is used to output a stage transmission signal and a gate driving signal in response to the voltage on the drive control node. The N cascaded gate driving modules are physically divided into multiple driving regions. The pre-charge unit of the first-stage gate driving module in each driving region is connected to at least one pre-charge trigger signal source and is configured to pre-charge the drive control node of the current stage in response to the pre-charge trigger signal provided by the pre-charge trigger signal source. The pre-charge unit of the non-first-stage gate driving module in the same driving region is connected to the stage transmission output terminal of the upper-stage gate driving module and is configured to pre-charge the drive control node of the current stage in response to the stage transmission signal output by the upper-stage gate driving module.

[0007] Optionally, the precharge trigger signal source includes a frame start signal line and a precharge control signal line; the plurality of driving regions include a first driving region close to the signal source, a third driving region far from the signal source, and a second driving region located between the first driving region and the third driving region; the precharge unit of the first-stage gate driving module of the first driving region is connected to the frame start signal line and is configured to: precharge the current stage driving control node in response to the frame start signal output by the frame start signal line; the precharge unit of the first-stage gate driving module of the second driving region is connected to the frame start signal line and the precharge control signal line respectively and is configured to: precharge the current stage driving control node in response to the precharge control signal output by the precharge control signal line. The drive control node of the third driving region is precharged; and in response to the frame start signal output by the frame start signal line, the precharge path of the current stage is pulled down for control; the precharge unit of the first-stage gate drive module of the third driving region is connected to the frame start signal line and the precharge control signal line respectively, and is configured to: simultaneously respond to the frame start signal and the precharge control signal to precharge the drive control node of the current stage; wherein, the frame start signal line outputs a valid frame start signal during the precharge phase of the first-stage gate drive module of the first driving region and the third driving region; the precharge control signal line outputs a valid precharge control signal during the precharge phase of the first-stage gate drive module of the second driving region and the third driving region.

[0008] Optionally, the pre-charge unit of the first-stage gate drive module of the first drive region includes: a first transistor, the control terminal of the first transistor being connected to the frame start signal line, the first terminal of the first transistor being connected to the power supply voltage terminal, and the second terminal of the first transistor being connected to the drive control node.

[0009] Optionally, the pre-charge unit of the first-stage gate drive module in the second driving region includes: a first transistor, the control terminal of the first transistor being connected to the stage output terminal of the upper-stage gate drive module, the first terminal of the first transistor being connected to the drive output terminal of the upper-stage gate drive module, and the second terminal of the first transistor being connected to the drive control node.

[0010] The second transistor has its control terminal connected to the precharge control signal line, its first terminal connected to its control terminal, and its second terminal connected to the drive control node; the third transistor has its control terminal connected to the frame start signal line, its first terminal connected to a low-level terminal, and its second terminal connected to the drive control node.

[0011] Optionally, the pre-charge unit of the first-stage gate driving module in the third driving region includes: a first transistor, the control terminal of which is connected to the stage output terminal of the upper-stage gate driving module, the first terminal of which is connected to the drive output terminal of the upper-stage gate driving module, and the second terminal of which is connected to the drive control node; and a second transistor, the control terminal of which is connected to the frame start signal line, the first terminal of which is connected to the pre-charge control signal line, and the second terminal of which is connected to the drive control node.

[0012] Optionally, the pre-charge unit of the first-stage gate driving module in each driving region includes: an auxiliary subunit connected to the stage transmission output terminal of the upper-stage gate driving module and an auxiliary node, configured to: charge the auxiliary node in response to the stage transmission signal output by the upper-stage gate driving module; a pre-charge subunit connected to the auxiliary node, a power supply voltage terminal, and the current-stage driving control node, configured to: transmit the voltage of the power supply voltage terminal to the driving control node in response to the voltage on the auxiliary node, so as to pre-charge the driving control node; and a reset subunit connected to the auxiliary node and the stage transmission output terminal of the lower-stage gate driving module, configured to: reset the auxiliary node in response to the stage transmission signal output by the lower-stage gate driving module; wherein the auxiliary node constitutes the pre-charge trigger signal source.

[0013] Optionally, the auxiliary sub-unit includes: a first transistor, the control terminal of which is connected to the stage output terminal of the upper i-th stage gate drive circuit, the first terminal of which is connected to the power supply voltage terminal, and the second terminal of which is connected to the first intermediate node; a first capacitor, the first terminal of which is connected to the first intermediate node, and the second terminal of which is connected to the second intermediate node; a second transistor, the control terminal of which is connected to the stage output terminal of the upper i+1-th stage gate drive circuit, the first terminal of which is connected to the first intermediate node, and the second terminal of which is connected to the auxiliary node; and a second capacitor, the first terminal of which is connected to the auxiliary node, and the second terminal of which is connected to the second intermediate node.

[0014] Optionally, the pre-charge sub-unit includes: a third transistor, the control terminal of which is connected to the auxiliary node, the first terminal of which is connected to the power supply voltage terminal, and the second terminal of which is connected to the second intermediate node; and a fourth transistor, the control terminal of which and the first terminal of which are connected to the second intermediate node, and the second terminal of which is connected to the drive control node.

[0015] Optionally, the auxiliary sub-unit includes: a first transistor, the control terminal of which is connected to the stage output terminal of the upper i-stage gate drive circuit, the first terminal of which is connected to the power supply voltage terminal, the second terminal of which is connected to the auxiliary node; and a first capacitor, the first terminal of which is connected to the auxiliary node, and the second terminal of which is connected to the second intermediate node.

[0016] Optionally, the precharge sub-unit includes: a third transistor, the control terminal of which is connected to the auxiliary node, the first terminal of which is connected to the precharge control signal line, and the second terminal of which is connected to the second intermediate node; and a fourth transistor, the control terminal of which and the first terminal of which are connected to the second intermediate node, and the second terminal of which is connected to the drive control node.

[0017] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes a gate driving circuit, and the drive output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0018] The technical solutions provided in this application have at least the following beneficial effects: This application divides the cascaded gate drive modules into multiple drive regions in terms of physical layout, and sets a pre-charge unit connected to at least one pre-charge trigger signal source at the first stage of each drive region. This allows the drive control node of the first-stage gate drive module to pre-charge in response to the high-quality pre-charge trigger signal provided by the pre-charge trigger signal source; while non-first-stage gate drive modules in the same drive region rely on the cascade signal from the previous stage for pre-charge. Therefore, the first-stage module of each drive region in this application obtains sufficient pre-charge charge through an independent pre-charge trigger signal source, thereby outputting a cascade signal with a good waveform. This restores a high-quality cascade chain within the region, effectively improving the problem of insufficient pre-charge of the drive control node due to cascade signal degradation. This ensures that the drive control nodes of each drive region from the near end to the far end can obtain sufficient and stable pre-charge, guaranteeing the consistency of the cascade signal across the entire screen. Ultimately, this improves the problem of uneven brightness caused by the drop in charging voltage of far-end pixels and the gradual decrease in brightness from the near end to the far end, significantly improving the display uniformity and long-term reliability of the elongated display screen. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0021] Figure 2 The diagram shown is a partitioning schematic provided in an embodiment of this application.

[0022] Figure 3 The figure shown is a timing diagram provided in an embodiment of this application.

[0023] Figure 4 The diagram shown is a circuit diagram of the pre-charge unit of the first-stage gate driving module of the first driving region provided in an embodiment of this application.

[0024] Figure 5 The diagram shown is a circuit diagram of the pre-charge unit of the first-stage gate drive module of the second driving region provided in an embodiment of this application.

[0025] Figure 6 The diagram shown is a circuit diagram of the pre-charge unit of the first-stage gate drive module of the third driving region provided in an embodiment of this application.

[0026] Figure 7 The diagram shown is a circuit diagram of a pre-charge unit of a first-stage gate drive module for each drive region provided in an embodiment of this application.

[0027] Figure 8 The diagram shown is another timing diagram provided by an embodiment of this application.

[0028] Figure 9 The diagram shown is a circuit diagram of the precharge unit of the first-stage gate drive module for each drive region provided in an embodiment of this application.

[0029] Figure 10 The diagram shown is another timing diagram provided in an embodiment of this application.

[0030] Explanation of reference numerals in the attached figures: 100. Gate drive module; 110. Precharge unit; 120. Output unit; 111. Auxiliary subunit; 112. Precharge subunit; 113. Reset subunit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; Q, drive control node; A, auxiliary node; B1, first intermediate node; B2, second intermediate node; CF, precharge trigger signal source; STV, frame start signal line; SW, precharge control signal line; VDD, power supply voltage terminal; VSS, low level terminal. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0033] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0034] Figure 1 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application. The gate driving circuit of this embodiment includes N cascaded gate driving modules 100, and each gate driving module 100 includes at least a drive control node Q, a precharge unit 110 and an output unit 120.

[0035] The pre-charge unit 110 is connected to the drive control node Q and is used to pre-charge the drive control node Q at the start of each frame scan or at the trigger of each stage, raising its potential to a level sufficient to turn on the output unit 120. The output unit 120 responds to the voltage on the drive control node Q by outputting the clock signal as the gate drive signal of this stage to the pixel array, and also outputting the clock signal as a stage transmission signal to the input terminal of the gate drive module 100 of the next stage or multiple stages below.

[0036] In this embodiment, all N cascaded gate driving modules 100 are divided into multiple driving regions in the physical layout of the display panel, and each driving region contains a continuous multi-level gate driving module 100; such as Figure 2 As shown, the partitioning method can be based on the physical location sequence of the modules, such as a region near the drive signal source (near end), a region far from the drive signal source (far end), and an intermediate region. The number of partitioned drive regions can be two, three, or more. Figure 2 In the text, AA represents the display area, GOA represents the gate drive circuit, COF represents the flip-chip film, and PCB board represents the printed circuit board.

[0037] Within the same driving region of this embodiment, the first-stage gate driving module 100 and the pre-charge units 110 of the other non-first-stage gate driving modules 100 have different signal connection configurations, specifically: (1) The precharge unit 110 of the first-stage gate drive module 100 in each drive region is connected to at least one precharge trigger signal source CF and is configured to precharge the drive control node Q of the current stage in response to the precharge trigger signal provided by the precharge trigger signal source CF. That is, its precharge unit 110 does not depend on the upper-level transmission signal within this region, but is connected to at least one independent precharge trigger signal source CF. The precharge trigger signal source CF is independent of the transmission signal chain of this region and can be the frame start signal line STV, the precharge control signal line SW, or an auxiliary node A generated within this stage. The function of the precharge trigger signal source CF in this embodiment is to provide the first-stage module with a higher quality precharge trigger signal that is independent of the upper-level transmission signal within this stage region, thereby ensuring that the drive control node Q of the first-stage gate drive module 100 can obtain sufficient and stable precharge charge.

[0038] (2) The pre-charge unit 110 of the non-first-stage gate drive module 100 in the same driving region is connected to the stage transmission output terminal Fn of the upper-stage gate drive module 100 and is configured to pre-charge the drive control node Q of the current stage in response to the stage transmission signal output by the upper-stage gate drive module 100. That is, its pre-charge unit 110 is only connected to the stage transmission output terminal Fn of the upper-stage gate drive module 100, which is to follow the cascade pre-charge method of related technologies. When the quality of the upper-stage stage transmission signal is good, this connection method is sufficient to meet the pre-charge requirements; when the stage transmission signal gradually deteriorates, this connection method will become the source of a vicious cycle.

[0039] Here, the gate drive circuit is divided into the following sections: Figure 2 The three driving regions shown are: the first driving region near the signal source, the second driving region, and the third driving region far from the signal source. The working principle of the gate driving circuit in this embodiment is as follows: (1) At the start of the frame, the precharge unit 110 of the first stage module of the first driving region receives the precharge trigger signal provided by the precharge trigger signal source CF, precharges the current stage drive control node Q, and the output unit 120 outputs high-quality stage transmission signal and gate drive signal.

[0040] (2) When the stage transmission signal reaches the end of the first driving region, the waveform has degraded to a certain extent. At this time, the first-stage module of the second driving region does not directly use the degraded stage transmission signal at the end of the first driving region, but receives the precharge trigger signal provided by the precharge trigger signal source CF through its precharge unit 110, and fully precharges the drive control node Q of the current stage, thereby restoring the stage transmission signal quality at the beginning of the region. The first-stage module of the second driving region outputs a high-quality stage transmission signal, which is then transmitted stage by stage in other stages within the region.

[0041] (3) Similarly, the first-stage gate drive module 100 in the third drive region also receives the precharge trigger signal provided by the precharge trigger signal source CF, and recharges again to restore signal quality.

[0042] In summary, this application divides the cascaded gate driving modules 100 into multiple driving regions in terms of physical layout, and sets a pre-charge unit 110 connected to at least one pre-charge trigger signal source CF at the first stage of each driving region. This allows the driving control node Q of the first-stage gate driving module 100 to pre-charge in response to the high-quality pre-charge trigger signal provided by the pre-charge trigger signal source CF; while the non-first-stage gate driving modules 100 in the same driving region rely on the cascade transmission signal from the upper stage for pre-charge. Therefore, the first-stage module of each driving region in this application obtains sufficient pre-charge charge through an independent pre-charge trigger signal source CF, thereby outputting a cascade transmission signal with a good waveform. High-quality cascade transmission is restored within the region, effectively improving the problem of insufficient pre-charge of the driving control node Q due to the degradation of the cascade transmission signal. This ensures that the driving control nodes Q of each driving region from the near end to the far end can obtain sufficient and stable pre-charge, guaranteeing the consistency of the cascade transmission signal across the entire screen. Ultimately, this improves the problem of uneven brightness caused by the decrease in charging voltage of far-end pixels and the gradual decay of brightness from the near end to the far end, significantly improving the display uniformity and long-term reliability of the elongated display screen.

[0043] In one specific implementation of the gate drive circuit of this application: the precharge trigger signal source CF specifically includes a frame start signal line STV that provides a frame start signal and a precharge control signal line SW that provides a precharge control signal, and the multiple drive regions specifically include a first drive region close to the signal source, a third drive region far from the signal source, and a second drive region located between the first drive region and the third drive region.

[0044] To achieve independent pre-charge for each partition, the output timing of the frame start signal line STV and the pre-charge control signal line SW in this embodiment is as follows: Figure 3 As shown: (1) The frame start signal line STV outputs a valid frame start signal (such as a high level) during the pre-charge phase of the first gate drive module 100 in the first drive region and during the pre-charge phase of the first gate drive module 100 in the third drive region.

[0045] (2) The precharge control signal line SW outputs a valid precharge control signal (such as a high level) during the precharge phase of the first gate drive module 100 in the second drive region and during the precharge phase of the first gate drive module 100 in the third drive region.

[0046] In other words: the first-stage gate drive module 100 of the first drive partition is triggered only by the frame start signal; the first-stage gate drive module 100 of the second drive partition is triggered only by the precharge control signal; the first-stage gate drive module 100 of the third drive partition is triggered simultaneously by the frame start signal and the precharge control signal; and the frame start signal and the precharge control signal need to be coordinated with multiple clock signals in terms of timing. In this embodiment, each drive region is partitioned in multiples of the number of clock signals; for example, taking 8 clock signals as an example, the number of stages of the gate drive module 100 in each drive region is a multiple of 8, such as 80 stages, 240 stages, etc.

[0047] Figure 4 The diagram shown is a circuit diagram of the pre-charge unit 110 of the first-stage gate driving module 100 of the first driving region provided in an embodiment of this application; as shown Figure 4 As shown, the precharge unit 110 includes a first transistor T1. The control terminal of the first transistor T1 is connected to the frame start signal line STV. The first terminal of the first transistor T1 is connected to the power supply voltage terminal VDD. The second terminal of the first transistor T1 is connected to the drive control node Q.

[0048] according to Figure 3 As shown in the timing diagram, during the pre-charging phase of the first-stage gate drive module 100 in the first driving region, the frame start signal line STV outputs a high-level frame start signal, the first transistor T1 is turned on, and the DC voltage output from the power supply voltage terminal VDD pre-charges the drive control node Q, causing the potential of the drive control node Q to rise rapidly, thereby turning on the output unit 120 and preparing to output the stage transmission signal and the gate drive signal. Since the first driving region is close to the signal source, the stage transmission signal has not yet degraded significantly. Therefore, only one first transistor T1 and the frame start signal are needed to complete reliable pre-charging, thereby reducing costs and saving layout area.

[0049] Figure 5 The diagram shown is a circuit schematic of the pre-charge unit 110 of the first-stage gate driving module 100 of the second driving region according to an embodiment of this application; as shown Figure 5As shown, the precharge unit 110 in this embodiment includes a first transistor T1, a second transistor T2, and a third transistor T3. Specifically, the control terminal of the first transistor T1 is connected to the stage transmission output terminal Fn-4 of the upper-level gate drive module 100 (taking the above four stages as an example), the first terminal of the first transistor T1 is connected to the drive output terminal Gn-4 of the upper-level gate drive module 100, and the second terminal of the first transistor T1 is connected to the drive control node Q; the control terminal of the second transistor T2 is connected to the precharge control signal line SW, the first terminal of the second transistor T2 is connected to the control terminal of the second transistor T2 (diode connection method), and the second terminal of the second transistor T2 is connected to the drive control node Q; the control terminal of the third transistor T3 is connected to the frame start signal line STV, the first terminal of the third transistor T3 is connected to the low-level terminal VSS, and the second terminal of the third transistor T3 is connected to the drive control node Q.

[0050] It should be noted that the function of the first transistor T1 in this embodiment is to maintain load matching with the non-first-stage gate drive module 100. That is, by retaining the same pre-charge path structure as the non-first-stage module, the input load of the first-stage module is basically consistent with that of the non-first-stage module, avoiding the introduction of new timing deviations due to differences in circuit structure. However, the actual pre-charge path in this embodiment is implemented through the second transistor T2, and the third transistor T3 is used to implement pull-down control.

[0051] This combination Figure 3 The timing diagram shown below illustrates the working principle of the precharge unit 110 in this embodiment: (1) Pre-charge process: The pre-charge control signal line SW outputs a high-level pre-charge control signal, and the second transistor T2 is turned on. The high-level pre-charge control signal pre-charges the drive control node Q. At the same time, the first transistor T1 also receives the upper-level transmission signal and turns on, and charges the drive control node Q through the upper-level gate drive signal. Since the upper-level transmission signal and the upper-level gate drive signal may have deteriorated to some extent, they are not used as the main pre-charge path here. At this time, the third transistor T3 is turned off because the frame start signal is low.

[0052] (2) Crosstalk prevention process: During the initial pre-charging stage of the subsequent third driving region, the pre-charging control signal line SW will output a high-level pre-charging control signal again. If the first stage of the second driving region receives this high-level pre-charging control signal at this time, it will generate unexpected pre-charging, leading to display abnormalities. Therefore, crosstalk risk needs to be considered in this embodiment. To solve this problem, this embodiment adopts two measures: ① Clock Phase Shift: The clock signal corresponding to the pre-charge of the first stage in the third driving region is configured with a specific phase. When the pre-charge control signal of the third driving region arrives, the clock signal transmitted to the first stage of the second driving region is at a low level. Even if the pre-charge unit 110 of the first stage of the second driving region generates pre-charge due to the pre-charge control signal, since the clock signal connected to its output terminal is at a low level, this stage cannot output a valid high pulse waveform, thereby avoiding erroneous output.

[0053] ② Adding a pull-down transistor: In this embodiment, a third transistor T3 is added to the first-stage pre-charge unit 110 of the second driving region. During the pre-charge stage of the first stage of the third driving region, the frame start signal line STV synchronously outputs a valid frame start signal, causing the third transistor T3 to conduct and pull down the first-stage drive control node Q of the second driving region to the low-level end VSS. Since the pre-charge path through the second transistor T2 is also working at this time, but the strength of the pull-down path is sufficient to offset the pull-up effect of the second transistor T2, the drive control node Q is locked at a low potential, preventing false pre-charge in the first stage of the second driving region.

[0054] Therefore, the second driving region is located in the middle section, and the transmission signal has degraded to some extent. By introducing a precharge control signal as an independent precharge trigger source, the first-stage driving control node Q in the current region is ensured to receive sufficient precharge. At the same time, load matching is achieved by retaining the first transistor T1, and comprehensive anti-crosstalk protection is achieved through clock phase misalignment and the pull-down effect of the third transistor T3.

[0055] Figure 6 The diagram shown is a circuit diagram of the pre-charge unit 110 of the first-stage gate drive module 100 in a third driving region according to an embodiment of this application; as shown Figure 6 As shown, the precharge unit 110 in this embodiment includes a first transistor T1 and a second transistor T2. The control terminal of the first transistor T1 is connected to the stage transmission output terminal Fn-4 of the upper-level gate driving module 100 (taking the above four stages as an example), the first terminal of the first transistor T1 is connected to the drive output terminal Gn-4 of the upper-level gate driving module 100, and the second terminal of the first transistor T1 is connected to the drive control node Q; the control terminal of the second transistor T2 is connected to the frame start signal line STV, the first terminal of the second transistor T2 is connected to the precharge control signal line SW, and the second terminal of the second transistor T2 is connected to the drive control node Q.

[0056] It should be noted that, similar to the second driving region, the first transistor T1 in this embodiment also serves to maintain load matching with other normal stages (non-first stage) to ensure circuit consistency. The second transistor T2 is the core path for pre-charging.

[0057] This combination Figure 3The timing diagram shown illustrates the working principle of the precharge unit 110 in this embodiment: At this time, the frame start signal line STV outputs a high-level frame start signal, and simultaneously, the precharge control signal line SW outputs a high-level precharge control signal. The second transistor T2 is turned on, and the high-level precharge control signal precharges the current stage's drive control node Q. At this time, the first transistor T1 also receives the signal transmitted from the upper stage and turns on, but this signal has been severely degraded after long-distance transmission and cannot provide effective precharge for the drive control node Q; therefore, it is not used as the main precharge path.

[0058] In this embodiment, the third driving region is located at the far end. The cascaded signal has been severely degraded after being transmitted over a long distance, making it impossible to effectively precharge using the cascaded signal from the previous stage. By simultaneously acting on the frame start signal and the precharge control signal, the second transistor T2 directly injects the high level of the precharge control signal into the driving control node Q, achieving strong precharge and restoring the cascaded signal in the far-end region, thus ensuring uniformity of the full-screen display.

[0059] It should be noted that the above embodiment divides the gate driving circuit into only three driving regions, which is too few. This results in a good pre-charge effect for the first row of each region, but a significant difference between the pre-charge effect of the first row and the last row of the previous region, which may produce bright lines on the display. To address this issue, this embodiment provides another specific implementation of the gate driving circuit: Unlike the aforementioned scheme that relies on external frame start signal line STV and pre-charge control signal line SW, the pre-charge unit 110 of the first-stage gate driving module 100 of each driving region in this embodiment uses an auxiliary node A generated by the charging of the previous stage transmission signal as the pre-charge trigger signal source CF through an internal bootstrap boost circuit. The high voltage of the boosted auxiliary node A is used to enhance the pre-charge capability of the driving control node Q. Therefore, the number of driving regions in this embodiment can be several, such as 10 or 20.

[0060] Figure 7 The diagram shown is a circuit schematic of a pre-charge unit 110 of a first-stage gate drive module 100 for each drive region, provided in an embodiment of this application. Figure 7 As shown, in this embodiment, the pre-charge unit 110 of the first-stage gate drive module 100 in each drive region includes three functional sub-units: an auxiliary sub-unit 111, a pre-charge sub-unit 112, and a reset sub-unit 113. Specifically, the auxiliary sub-unit 111 is connected to the stage transmission output terminal of the upper-stage gate drive module 100 and the auxiliary node A, respectively. During the pre-charge preparation stage, in response to the stage transmission signals output by the previous several stages (e.g., the upper 4 stages, the upper 3 stages), it performs time-division charging of the auxiliary node A, providing a basis for subsequent bootstrap voltage boosting.

[0061] The pre-charge sub-unit 112 is connected to the auxiliary node A, the power supply voltage terminal VDD, and the current stage drive control node Q. Its function is to transmit the voltage of the power supply voltage terminal VDD to the drive control node Q in response to the voltage on the auxiliary node A, thereby pre-charging the drive control node Q.

[0062] The reset subunit 113 is connected to both the auxiliary node A and the stage transmission output terminal of the lower-level gate drive module 100. Its function is to pull the auxiliary node A down to a low level in response to the stage transmission signal output by the lower-level gate drive module 100 after the current stage precharge and output are completed, so that it can start working again in the next frame.

[0063] Here, combined with Figure 7 circuit structure and Figure 8 Based on the timing diagram, the pre-charge unit 110 of this embodiment is described as follows: (1) such as Figure 7 As shown, the auxiliary subunit 111 in this embodiment includes a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, and a first intermediate node B1 and a second intermediate node B2. Specifically, the control terminal of the first transistor T1 is connected to the stage transmission output terminal of the upper i-stage gate drive module 100 (e.g., Figure 7 In Fn-4), the first terminal of the first transistor T1 is connected to the power supply voltage terminal VDD, and the second terminal of the first transistor T1 is connected to the first intermediate node B1; the first terminal of the first capacitor C1 is connected to the first intermediate node B1, and the second terminal of the first capacitor C1 is connected to the second intermediate node B2; the control terminal of the second transistor T2 is connected to the stage transmission output terminal of the upper i+1 stage gate drive module 100 (e.g., Fn-4). Figure 7 In the second transistor T2 (Fn-3), the first terminal of the second transistor T2 is connected to the first intermediate node B1, and the second terminal of the second transistor T2 is connected to the auxiliary node A; the first terminal of the second capacitor C2 is connected to the auxiliary node A, and the second terminal of the second capacitor C2 is connected to the second intermediate node B2.

[0064] During the pre-charge phase, the signal is first transmitted to the i-th stage (e.g., Figure 7 When the stage transfer signal (output of Fn-4 in the middle) arrives, the first transistor T1 turns on, and the DC voltage output from the power supply voltage terminal VDD charges the first capacitor C1 through the first transistor T1. The first capacitor C1 stores charge, and the potential of the first intermediate node B1 rises. Subsequently, the stage transfer signal of the upper i-1 stage (such as...) arrives. Figure 7When the stage transmission signal output by Fn-3 arrives, the second transistor T2 turns on. At this time, the charge stored in the first capacitor C1 is transferred to the second capacitor C2 through the second transistor T2, charging the auxiliary node A. The purpose of this is to give the first capacitor C1 sufficient charging time, and after the first capacitor C1 is fully charged, the charge is quickly released to the second capacitor C2 and the auxiliary node A through the second transistor T2, thereby ensuring that the auxiliary node A obtains the highest possible initial voltage.

[0065] (2) For example Figure 7 As shown, the pre-charge sub-unit 112 in this embodiment includes a third transistor T3 and a fourth transistor T4. Specifically, the control terminal of the third transistor T3 is connected to the auxiliary node A, the first terminal of the third transistor T3 is connected to the power supply voltage terminal VDD, and the second terminal of the third transistor T3 is connected to the second intermediate node B2; the control terminal and the first terminal of the fourth transistor T4 are connected to the second intermediate node B2 (diode connection), and the second terminal of the fourth transistor T4 is connected to the drive control node Q.

[0066] Once auxiliary node A is charged to a certain voltage, the third transistor T3 turns on, transmitting the power supply voltage output from the power supply voltage terminal VDD to the second intermediate node B2. Simultaneously, the fourth transistor T4, due to its diode connection, turns on, transmitting the voltage from the second intermediate node B2 to the drive control node Q, initiating pre-charging of drive control node Q.

[0067] The key is that in subsequent stages (e.g., when the output unit 120 starts working, the clock signal jumps to a high level), the potential of auxiliary node A is further raised through the bootstrap effect of the second capacitor C2. Specifically, since the other end of the second capacitor C2 is connected to the second intermediate node B2, and the potential of the second intermediate node B2 rises with the output process (because the fourth transistor T4 is turned on, the voltage of the drive control node Q will bootstrap), through capacitive coupling, auxiliary node A is pumped up to a maximum voltage Vmax much higher than the power supply voltage VDD. At this time, the gate voltage of the third transistor T3 reaches Vmax, causing it to be deeply turned on, allowing the power supply voltage VDD to continuously charge the drive control node Q with a large current, thus achieving a higher pre-charge voltage and a longer pre-charge time.

[0068] (3) such as Figure 7 As shown, the reset subunit 113 in this embodiment includes a fifth transistor T5. The control terminal of the fifth transistor T5 is connected to the stage output terminal of the next-stage gate drive module 100 (e.g., the stage output terminal Fn+4 of the (n+4)th stage), the first terminal of the fifth transistor T5 is connected to the low-level terminal VSS, and the second terminal of the fifth transistor T5 is connected to the auxiliary node A.

[0069] After the pre-charge and output of this stage are completed, the auxiliary node A needs to be reset to avoid residual charge affecting the operation of the next frame. When the next gate drive module 100 outputs a signal (i.e., when the next row scan begins), the signal is applied to the gate of the fifth transistor T5, which turns on and pulls the auxiliary node A down to the low level VSS, thereby clearing the charge of the auxiliary node A and preparing it for the pre-charge of the next frame.

[0070] This embodiment uses an internal bootstrap boost circuit to actively pump the potential of auxiliary node A (i.e., precharge trigger signal source CF) to a maximum voltage Vmax higher than the power supply voltage VDD, thereby enabling the third transistor T3 in the precharge subunit 112 to be deeply turned on, allowing the power supply voltage VDD to charge the drive control node Q for a long time with a large current, overcoming the problem of deteriorated waveform of the preceding stage transmission signal and inability to effectively precharge the drive control node Q.

[0071] Figure 9 The diagram shown is a circuit schematic of the pre-charge unit 110 of the first-stage gate drive module 100 for each drive region provided in an embodiment of this application; as shown Figure 9 As shown, the auxiliary subunit 111 in this embodiment includes a first transistor T1 and a first capacitor C1. The control terminal of the first transistor T1 is connected to the stage output terminal of the upper i-stage gate drive module 100 (e.g., Figure 9 In Fn-4 (taking the above four stages as an example), the first terminal of the first transistor T1 is connected to the power supply voltage terminal VDD, and the second terminal of the first transistor T1 is connected to the auxiliary node A; the first terminal of the first capacitor C1 is connected to the auxiliary node A, and the second terminal of the first capacitor C1 is connected to the second intermediate node B2.

[0072] It should be noted that, with Figure 7 The circuit structure shown is different; in this embodiment, auxiliary node A is directly charged only by the first transistor T1. When the transmission signal from the upper 4th stage arrives, the first transistor T1 turns on, and the power supply voltage VDD charges auxiliary node A through the first transistor T1, while simultaneously coupling to the second intermediate node B2 through the first capacitor C1. Since there is no... Figure 7 In the time-division multiplexing process of the second transistor T2 and the second capacitor C2, the initial voltage of the auxiliary node A is the power supply voltage VDD (minus the transistor threshold voltage drop), rather than the voltage after two transfers. This simplifies the circuit structure, but the initial voltage of the auxiliary node A is slightly lower than... Figure 7 The initial voltage is shown, and the voltage timing of auxiliary node A is as follows: Figure 10 As shown.

[0073] like Figure 9As shown, the precharge subunit 112 in this embodiment includes a third transistor T3 and a fourth transistor T4. The control terminal of the third transistor T3 is connected to the auxiliary node A, the first terminal of the third transistor T3 is connected to the precharge control signal line SW, and the second terminal of the third transistor T3 is connected to the second intermediate node B2; the control terminal and the first terminal of the fourth transistor T4 are connected to the second intermediate node B2 (diode connection), and the second terminal of the fourth transistor T4 is connected to the drive control node Q.

[0074] This combination Figure 10 The timing diagram shown illustrates the working principle of this embodiment as follows: When auxiliary node A is charged to a high potential, the third transistor T3 is turned on. At this time, a valid precharge control signal (such as a high level) is output on the precharge control signal line SW. The high-level precharge control signal is transmitted to the second intermediate node B2 through the turned-on third transistor T3, and then transmitted to the drive control node Q through the diode-connected fourth transistor T4, thereby precharging the drive control node Q.

[0075] Subsequently, the bootstrap boost stage begins: when the clock signal transitions to a high level, the output unit 120 of this stage starts operating, driving the control node Q to bootstrap and raise its potential. Since the first capacitor C1 is connected between the auxiliary node A and the second intermediate node B2, and the potential of the second intermediate node B2 increases as the drive control node Q rises, the potential of the auxiliary node A is further boosted to a maximum voltage Vmax higher than the power supply voltage VDD through the coupling effect of the first capacitor C1. At this time, the gate voltage of the third transistor T3 reaches Vmax, enabling it to conduct deeply, allowing the precharge control signal to continuously charge the drive control node Q with a large current.

[0076] Finally, it should be noted that, as Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 9 In the circuit structure shown, the output unit 120 includes a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. The sixth transistor T6 is used for output stage signal transmission, and the seventh transistor T7 is used for outputting the gate drive signal. The operating principle of the output unit 120 is the same as related technologies and will not be described again here. Furthermore, the gate drive circuit of this embodiment also includes a reset module for resetting the drive control node Q, a pull-down module for pulling down the drive control node Q and the drive output terminal, and a noise reduction module for reducing noise at the drive control node Q, the stage transmission output terminal, and the drive output terminal. Additionally, Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 9In the diagram, Fn represents the nth stage transmission output terminal, Gn represents the nth stage drive output terminal, Fn-4 represents the (n-4)th stage transmission output terminal, Fn+4 represents the (n+4)th stage transmission output terminal, Fn-3 represents the (n-3)th stage transmission output terminal, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, CK1 represents the first clock signal, and CK6 represents the sixth clock signal.

[0077] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes the gate driving circuit described in any of the above embodiments, wherein the drive output terminal of the gate driving module 100 in the gate driving circuit is electrically connected to at least one scan line.

[0078] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0079] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0080] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The system includes N cascaded gate drive modules. Each gate drive module includes at least a drive control node, a pre-charge unit and an output unit connected to the drive control node. The pre-charge unit is used to pre-charge the drive control node, and the output unit is used to output a stage transmission signal and a gate drive signal in response to the voltage on the drive control node. The N cascaded gate driving modules are physically divided into multiple driving regions; the multiple driving regions include a first driving region close to the signal source, a third driving region far from the signal source, and a second driving region located between the first driving region and the third driving region. In this context, the precharge unit of the first-stage gate drive module of each drive region is connected to at least one precharge trigger signal source and is configured to: precharge the current stage drive control node in response to the precharge trigger signal provided by the precharge trigger signal source; The pre-charge unit of the non-first-level gate drive module in the same drive region is connected to the stage transmission output terminal of the upper-level gate drive module and is configured to: pre-charge the drive control node of the current level in response to the stage transmission signal output by the upper-level gate drive module. The precharge trigger signal source includes a frame start signal line and a precharge control signal line; the precharge unit of the first-stage gate drive module of the first drive region is connected to the frame start signal line and is configured to: precharge the current stage drive control node in response to the frame start signal output by the frame start signal line. The precharge unit of the first-stage gate drive module of the second drive region is connected to the frame start signal line and the precharge control signal line respectively, and is configured to: precharge the drive control node of the current stage in response to the precharge control signal output by the precharge control signal line; and pull down the precharge path of the current stage in response to the frame start signal output by the frame start signal line. The precharge unit of the first-stage gate drive module of the third drive region is connected to the frame start signal line and the precharge control signal line respectively, and is configured to: simultaneously respond to the frame start signal and the precharge control signal to precharge the drive control node of the current stage. Specifically, the frame start signal line outputs a valid frame start signal during the pre-charge phase of the first-stage gate drive module in the first drive region and the third drive region; the pre-charge control signal line outputs a valid pre-charge control signal during the pre-charge phase of the first-stage gate drive module in the second drive region and the third drive region.

2. The gate driving circuit according to claim 1, characterized in that, The pre-charge unit of the first-stage gate drive module in the first driving region includes: The first transistor has its control terminal connected to the frame start signal line, its first terminal connected to the power supply voltage terminal, and its second terminal connected to the drive control node.

3. The gate driving circuit according to claim 1, characterized in that, The pre-charge unit of the first-stage gate drive module in the second driving region includes: The first transistor has a control terminal connected to the stage output terminal of the upper gate drive module, a first terminal connected to the drive output terminal of the upper gate drive module, and a second terminal connected to the drive control node. The second transistor has its control terminal connected to the precharge control signal line, its first terminal connected to its control terminal, and its second terminal connected to the drive control node. The third transistor has its control terminal connected to the frame start signal line, its first terminal connected to a low-level terminal, and its second terminal connected to the drive control node.

4. The gate driving circuit according to claim 1, characterized in that, The pre-charge unit of the first-stage gate drive module in the third driving region includes: The first transistor has a control terminal connected to the stage output terminal of the upper gate drive module, a first terminal connected to the drive output terminal of the upper gate drive module, and a second terminal connected to the drive control node. The second transistor has its control terminal connected to the frame start signal line, its first terminal connected to the precharge control signal line, and its second terminal connected to the drive control node.

5. The gate driving circuit according to claim 1, characterized in that, The pre-charge unit of the first-stage gate drive module in each of the said drive regions includes: An auxiliary subunit, connected to the stage transmission output terminal of the upper-level gate drive module and an auxiliary node respectively, is configured to charge the auxiliary node in response to the stage transmission signal output by the upper-level gate drive module. The pre-charge sub-unit, which is connected to the auxiliary node, the power supply voltage terminal and the current stage drive control node respectively, is configured to: in response to the voltage on the auxiliary node, transmit the voltage of the power supply voltage terminal to the drive control node to pre-charge the drive control node; The reset subunit, which is connected to the auxiliary node and the stage transmission output terminal of the lower-level gate drive module respectively, is configured to reset the auxiliary node in response to the stage transmission signal output by the lower-level gate drive module. The auxiliary node constitutes the precharge trigger signal source.

6. The gate driving circuit according to claim 5, characterized in that, The auxiliary subunit includes: The first transistor has its control terminal connected to the stage output terminal of the upper i-stage gate drive circuit, its first terminal connected to the power supply voltage terminal, and its second terminal connected to the first intermediate node. A first capacitor, wherein a first terminal of the first capacitor is connected to the first intermediate node, and a second terminal of the first capacitor is connected to the second intermediate node; The second transistor has its control terminal connected to the stage output terminal of the upper i+1 stage gate drive circuit, its first terminal connected to the first intermediate node, and its second terminal connected to the auxiliary node. The second capacitor has its first end connected to the auxiliary node and its second end connected to the second intermediate node.

7. The gate driving circuit according to claim 6, characterized in that, The pre-charge subunit includes: The third transistor has a control terminal connected to the auxiliary node, a first terminal connected to the power supply voltage terminal, and a second terminal connected to the second intermediate node. The fourth transistor has its control terminal and first terminal connected to the second intermediate node, and its second terminal connected to the drive control node.

8. The gate driving circuit according to claim 5, characterized in that, The auxiliary subunit includes: The first transistor has its control terminal connected to the stage output terminal of the upper i-stage gate drive circuit, its first terminal connected to the power supply voltage terminal, and its second terminal connected to the auxiliary node. A first capacitor, the first end of which is connected to the auxiliary node, and the second end of which is connected to the second intermediate node; The pre-charge subunit includes: The third transistor has its control terminal connected to the auxiliary node, its first terminal connected to the precharge control signal line, and its second terminal connected to the second intermediate node. The fourth transistor has its control terminal and first terminal connected to the second intermediate node, and its second terminal connected to the drive control node.

9. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-8, wherein the driving output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

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