Method of testing a semiconductor, test apparatus using the method and production method

Abstract

In a test method, first test operations are performed on semiconductor products mounted on a test board to determine whether each semiconductor product is normal or defective. The test board includes a plurality of test channels, and two or more semiconductor products share a single test channel. A test map representing results of the first test operations is generated. The test map is divided into a first region and a second region, and the first region identifies semiconductor products that share the same test channel and have been determined to be completely defective. The second region identifies semiconductor products other than those identified in the first region. Using information of the first region and the second region, a first probability model, and a second probability model, a second test operation is performed to determine whether defects of semiconductor products included in the first region are board-related defects caused by characteristics of the test board.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0011262, filed on January 24, 2025, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to a method for testing semiconductor products using probabilistic model-based testing, a test apparatus for performing the method for testing semiconductor products, and a method for producing semiconductor products using the method for testing semiconductor products. Background Technology

[0004] Semiconductor products can be manufactured on semiconductor wafers through several processes, such as oxidation, photolithography, etching, deposition, ion implantation, and metal wiring. Currently, most semiconductor products can be tested using automated test equipment (ATE) to improve the productivity of semiconductor production.

[0005] As a result of testing using automated testing equipment, some semiconductor products may be identified as defective due to defects in the semiconductor product itself or due to errors in the testing equipment. Because semiconductor products identified as defective due to errors in the testing equipment must be recovered through retesting, additional time, cost, and effort are usually required to distinguish between defects caused by errors in the testing equipment and defects in the semiconductor product itself. Summary of the Invention

[0006] At least one example embodiment of this disclosure provides a method for testing semiconductor products that can efficiently detect and address defects caused by errors on the test equipment using probabilistic model-based testing.

[0007] At least one example embodiment of this disclosure provides a test apparatus for performing a method of testing a semiconductor product.

[0008] At least one example embodiment of this disclosure provides a method for producing semiconductor products using a method for testing semiconductor products.

[0009] According to an example embodiment, a method for testing semiconductor products includes: performing a first test operation on a plurality of semiconductor products mounted on a test board to determine whether each of the plurality of semiconductor products is normal or defective, the test board including a plurality of test channels configured to receive test signals and two or more semiconductor products sharing a single test channel among the plurality of test channels; generating a test pattern based on a first result of the first test operation; dividing the test pattern into a first region and a second region based on channel layout data of the test board, the first region identifying semiconductor products among the plurality of semiconductor products that share the same test channel and have been determined to be completely defective, and the second region identifying semiconductor products other than those identified in the first region; and performing a second test operation using information from the first and second regions, a first probability model, and a second probability model to determine whether the defect of the semiconductor product identified in the first region is a board-related defect caused by characteristics of the test board.

[0010] According to an example embodiment, a testing device includes: a test board including multiple test channels for testing multiple semiconductor products mounted on the test board, each of the multiple test channels being configured to receive a test signal, and two or more semiconductor products sharing one of the multiple test channels; a first test module configured to perform a first test operation to determine whether each of the multiple semiconductor products is normal or defective, and to generate a test pattern representing the result of the first test operation; and a second test module configured to divide the test pattern into a first region and a second region based on channel layout data of the test board, and to perform a second test operation using information from the first region and the second region, a first probability model, and a second probability model to determine whether a defect in a semiconductor product included in the first region is a board-related defect caused by characteristics of the test board, wherein the first region identifies semiconductor products sharing the same test channel and having been determined to be completely defective, and the second region identifies semiconductor products other than those identified in the first region.

[0011] According to an example embodiment, a method of manufacturing semiconductor products includes: manufacturing a plurality of semiconductor products; and testing the plurality of semiconductor products mounted on a test board using a test device, the test board including a plurality of test channels for receiving test signals, wherein two or more semiconductor products share one of the plurality of test channels, wherein testing the plurality of semiconductor products includes: performing a first test operation to determine whether each of the plurality of semiconductor products mounted on the test board is normal or defective; generating a test map representing the result of the first test operation; dividing the test map into a first region and a second region based on channel layout data of the test board, the first region identifying semiconductor products sharing the same test channel and having been determined to be completely defective, the second region identifying semiconductor products other than those identified in the first region; and performing a second test operation using information from the first region and the second region, a first probability model, and a second probability model to determine whether the defect of the semiconductor product identified in the first region is a board-related defect caused by characteristics of the test board.

[0012] In the method, testing equipment, and method for manufacturing semiconductor products according to the example embodiments, a test pattern can be obtained by performing a first test operation on each of a plurality of semiconductor products using a test board with a channel-sharing structure. The test pattern can be divided into a first region and a second region using the channel layout data of the test board, and a second test operation can be performed using the divided regions and a predefined probability model to determine whether each defective semiconductor product determined to be defective by the first test operation has a board-related defect. Therefore, compared with conventional methods utilizing GPUs or servers, board-related defects can be detected and resolved with relatively less time and lower cost. Furthermore, the testing equipment can be fully automated and can detect and handle board-related defects autonomously without the need for additional GPUs or servers. Attached Figure Description

[0013] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1 This is a flowchart illustrating a method for testing a semiconductor product according to an example embodiment.

[0015] Figure 2 This is a block diagram illustrating a test apparatus according to an example embodiment.

[0016] Figure 3A , Figure 3B , Figure 3C and Figure 3D It is used to describe including Figure 2A diagram of the test board in the testing equipment.

[0017] Figure 4A and Figure 4B It is shown that it includes Figure 2 A block diagram of an example of the first and second test modules in the test equipment.

[0018] Figure 5 This is a block diagram illustrating a test apparatus according to an example embodiment.

[0019] Figure 6 Is to show execution Figure 1 The flowchart is an example of the second test operation.

[0020] Figure 7 This shows the output. Figure 6 A flowchart illustrating an example of the result value of the second test operation.

[0021] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C and Figure 9D This is a diagram used to describe a method for testing a semiconductor product according to an example embodiment.

[0022] Figure 10 This is a flowchart illustrating a method for testing a semiconductor product according to an example embodiment.

[0023] Figure 11A , Figure 11B and Figure 11C It is shown that it includes Figure 2 A block diagram of an example of the second test module in the test equipment.

[0024] Figure 12 This is a flowchart illustrating a method for testing a semiconductor product according to an example embodiment.

[0025] Figure 13 This is a block diagram illustrating a test apparatus according to an example embodiment.

[0026] Figure 14A and Figure 14B This is a block diagram illustrating an example of a semiconductor product according to an example embodiment.

[0027] Figure 15A and Figure 15B This is a diagram illustrating an example of a semiconductor product according to an example embodiment.

[0028] Figure 16 This is a flowchart illustrating a method for producing a semiconductor product according to an example embodiment. Detailed Implementation

[0029] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0030] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements or components, these elements or components should not be limited by these terms. Unless the context otherwise requires, these terms are used only to distinguish one element or component from another. Therefore, without departing from the teachings of the invention, a first element or component discussed in one part of the specification may be referred to as a second element or component in another part of the specification or in the claims. Furthermore, in some cases, even if the terms "first," "second," etc., are not used in the specification, they may still be referred to as "first" or "second" in the claims in order to distinguish the different claimed elements from each other.

[0031] It should be understood that when a component is referred to as being "connected to" another component or "attached to" another component, it can be directly connected to or on another component, or there may be an intermediate component.

[0032] Items described in the singular in this document may be provided in the plural. Therefore, unless the context otherwise indicates, a description of a single item provided in the plural should be understood to apply to the remaining multiple items.

[0033] Figure 1 This is a flowchart illustrating a method for testing a semiconductor product according to an example embodiment.

[0034] Reference Figure 1 A method for testing semiconductor products according to an example embodiment can be executed on a computer-based test apparatus, at least a portion of which is implemented in hardware and / or software. For example, the test apparatus may include a program (or program code) comprising a plurality of instructions executable by at least one processor. (See also...) Figure 2 , Figure 4A , Figure 4B and Figure 5 Describe an example configuration of the test equipment.

[0035] In the method for testing semiconductor products according to an example embodiment, a first test operation is performed to determine whether each of a plurality of semiconductor products is normal or defective (operation S100).

[0036] The semiconductor product to be tested can be a device under test (DUT). For example, the semiconductor product can be provided in the form of a semiconductor chip, and the semiconductor chip can be a memory chip with data storage capabilities. For example, the semiconductor product can be provided in the form of a semiconductor package comprising multiple semiconductor chips. (See also...) Figure 14A , Figure 14B , Figure 15A and Figure 15B Describes an example configuration for a semiconductor product.

[0037] The first test operation can be performed to determine whether each semiconductor product under test is a normal semiconductor product that operates normally or a defective semiconductor product that operates abnormally due to its defects. Common testing methods can be used to perform the first test operation. A test board with multiple semiconductor products mounted or equipped on it can be used to perform the first test operation.

[0038] The test board includes multiple test channels for receiving test signals used to test multiple semiconductor products. For example, each semiconductor product can communicate with the test equipment through a specific test channel associated with it. For instance, two or more semiconductor products mounted on the test board can share one of the multiple test channels. This structure can be called a channel-sharing structure, and a test board with a channel-sharing structure can be called a channel-sharing board. (See reference...) Figure 3A , Figure 3B , Figure 3C and Figure 3D Describes an example configuration of the test board and multiple test channels.

[0039] As a result of the first test operation, a test pattern can be generated, for example, based on the first test result of the first test operation (operation S200). For example, the test pattern may include information indicating whether each of the multiple semiconductor products on the test board is normal or defective. The test pattern can also be called a DUT diagram. (See reference...) Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C and Figure 9D Example describing a test graph.

[0040] Based on the channel layout data of the test board and the first test result, the test pattern is divided into a first region and a second region (operation S300). The channel layout data may include information associated with or related to the configuration of multiple test channels formed in the test board. The first region may identify semiconductor products that share the same test channel among multiple semiconductor products and have been determined to be completely defective, and the second region may identify semiconductor products other than those identified in the first region.

[0041] Using the information from the first and second regions, the first probability model, and the second probability model, a second test operation is performed to determine whether the defect in the semiconductor product identified by the first region is a board-related defect or a defect in the semiconductor product itself (operation S400). The first and second probability models can be predetermined or predefined. Unlike the first test operation, the second test operation can be an operation to determine whether the defect in each defective semiconductor product identified as defective during the first test operation is due to its own defect (e.g., whether it is a real defect or an inherent defect) or due to an operational error of the test board that is not a defect in the semiconductor product itself (e.g., whether it is a spurious defect).

[0042] In some example embodiments, a probability-based model support computation approach can be used to perform the second test operation. A probability-based model support computation approach can be a statistical method used to evaluate how well a given model fits the observed data by leveraging probability theory. This method typically includes at least the following steps: 1) Likelihood estimation; calculating the probability of the observed data under different models. This is typically done using maximum likelihood estimation (MLE), where model parameters are adjusted to maximize the likelihood of the data. 2) Model comparison; competing models are evaluated based on their likelihoods. A common approach is the likelihood ratio test, which compares the goodness of fit between two models by taking the likelihood ratio of the two models. 3) Bayesian inference: In some cases, a Bayesian approach is used to incorporate prior probabilities, where the posterior probability of the model is calculated based on the observed data and prior knowledge. 4) Support computation; the degree to which the model is supported by the data is quantified using statistical measures such as log-likelihood, Bayes factor, or information criterion. 5) Decision making; based on the calculated probabilities, a decision is made about which model best interprets the data. If the likelihood ratio or other statistical measures indicate a significant difference, one model may be superior to the other. For example, a second test operation can be performed based on the likelihood ratio test. (Refer to...) Figure 6 and Figure 7 Describe operation S400.

[0043] For mass production of semiconductor products, multiple semiconductor products can be mounted on a single test board, which is then installed in test equipment to perform testing. The test board may include multiple test channels, and the test equipment can apply test signals to the semiconductor products through these channels. Some semiconductor products may share a single test channel and receive test signals through it. In this scenario, due to abnormal arrangement or poor connections of the semiconductor products on a specific test channel, communication errors may occur between that channel and the corresponding semiconductor product. This can lead to the semiconductor product being identified as defective even if it is not inherently defective. Because this semiconductor product is identified as defective due to the characteristics of the test board, it can be determined to be normal when retested under standard test conditions. Defects caused by the characteristics of the test board can be described as board-related defects.

[0044] Traditionally, detecting and resolving board-related defects requires significant time and cost, and in some cases, testing equipment may not be able to independently identify and resolve these defects.

[0045] In the semiconductor product testing method according to the example embodiment, a test map can be generated by performing a first test operation on each of a plurality of semiconductor products using a test board with a channel-sharing structure. The test map can be divided into a first region and a second region using the channel layout data of the test board and the first test result from the first test operation. A second test operation can be performed to determine whether the defect of each semiconductor product identified as defective in the first test operation is due to a board-related defect or a defect in the semiconductor product itself. This evaluation is performed using information from the divided first and second regions and a predefined probability model. Therefore, compared with conventional methods utilizing graphics processing units (GPUs) or servers, board-related defects can be detected and resolved in a relatively short time and at a lower cost. Furthermore, the test equipment can be fully automated and can independently detect and resolve board-related defects without requiring additional GPUs or servers.

[0046] Figure 2 This is a block diagram illustrating a test apparatus according to an example embodiment.

[0047] Reference Figure 2 The test equipment 1000 includes a test board 1100, a first test module 1200, and a second test module 1300.

[0048] As is customary in the disclosed art, features and embodiments are described and illustrated in the accompanying drawings in the form of “modules.” Those skilled in the art will understand that modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, etc., which can be formed using semiconductor-based manufacturing processes or other production techniques. Where modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each module can be implemented using dedicated hardware, or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each module of the embodiments may be physically divided into two or more interactive and discrete modules. Furthermore, without departing from the scope of the inventive concept, the modules of the embodiments may be physically combined into more complex modules. A “module” can be, but is not limited to, software and / or hardware components performing certain tasks, such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). A "module" can be configured to reside in a tangible, addressable storage medium and to execute on one or more processors. For example, a "module" can include components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, routines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0049] Test board 1100 can be designed to accommodate multiple semiconductor products SC. Multiple semiconductor products SC mounted on test board 1100 can be tested simultaneously and / or sequentially. Test board 1100 includes multiple channels for receiving test signals and communicating with the multiple semiconductor products SC. (See reference...) Figure 3A , Figure 3B , Figure 3C and Figure 3D As described, two or more semiconductor products can share a single test channel.

[0050] In some example embodiments, the test board 1100 may be attachable and detachable. For example, while performing a test operation, the test board 1100 may be attached to the test equipment 1000 to test multiple semiconductor products SC, and the test board 1100 may be detached from the test equipment 1000 upon completion of testing the multiple semiconductor products SC. The test equipment 1000 may include a test board connector to which the test board 1100 is attached during a test operation, and to which the test board 1100 is detached when preparing for another test operation. For example, the test board 1100 may be detached from a test board connector used to mount semiconductor products to be tested.

[0051] although Figure 2 An example of a test apparatus 1000 including a test board 1100 is shown, but the example embodiment is not limited thereto. For example, as will be referred to Figure 13 As described, the test equipment may include multiple test boards and can test semiconductor products mounted on multiple test boards simultaneously and / or sequentially.

[0052] The first test module 1200 performs a first test operation to determine whether each of the plurality of semiconductor products SC mounted on the test board 1100 is normal or defective, and generates a test pattern reflecting the first test result of the first test operation.

[0053] The second test module 1300 divides the test pattern into a first region and a second region based on the channel layout data of the test board 1100. Based on information from the first and second regions, a first probability model, and a second probability model, it performs a second test operation to determine whether a defect in a semiconductor product within the first region is a board-related defect caused by characteristics of the test board 1100, or whether the defect is caused by a defect in the semiconductor product itself. The first region can identify semiconductor products that share the same test channel and have been determined to be completely defective, and the second region can identify semiconductor products other than those identified in the first region.

[0054] In some example embodiments, such as referring to Figure 5 As described, the test device 1000 may include a processor and a storage device (or storage medium). The first test module 1200 and the second test module 1300 may use the processor and storage device to perform a first test operation and a second test operation, respectively. Each of the first test module 1200 and the second test module 1300 may include a processor and a storage device.

[0055] As mentioned above, according to the reference Figure 1The described example embodiment, including test board 1100, first test module 1200, and second test module 1300, allows the test apparatus 1000 to perform semiconductor product testing using probabilistic model-based testing. For example, test board 1100 and first test module 1200 can perform... Figure 1 Operations S100 and S200 in the above steps can be executed by the second test module 1300. Figure 1 Operations S300 and S400 in the process.

[0056] In some example embodiments, the first test module 1200 and the second test module 1300 may be implemented as a single integrated module. In other example embodiments, the first test module 1200 and the second test module 1300 may be implemented as separate and distinct modules.

[0057] Figure 3A , Figure 3B , Figure 3C and Figure 3D It is used to describe including Figure 2 A diagram of the test board in the testing equipment.

[0058] Reference Figure 3A Multiple semiconductor products SC11, SC12, SC13, SC14, SC15, SC16, SC17, SC18, SC21, SC22, SC23, SC24, SC25, SC26, SC27, SC28, SC31, SC32, SC33, SC34, SC35, SC36, SC37, SC38, SC41, SC42, SC43, SC44, SC45, SC46, SC47, SC48, SC5 1. SC52, SC53, SC54, SC55, SC56, SC57, SC58, SC61, SC62, SC63, SC64, SC65, SC66, SC67, SC68, SC71, SC72, ​​SC73, SC74, SC75, SC76, SC77, SC78, SC81, SC82, SC83, SC84, SC85, SC86, SC87, and SC88 can be installed on test board 1100a.

[0059] Multiple semiconductor products SC11 to SC88 can be arranged and mounted in a two-dimensional (2D) matrix. For example, sixty-four semiconductor products SC11 to SC88 can be arranged to form eight rows R1, R2, R3, R4, R5, R6, R7, and R8 extending in a first direction D1 and eight columns C1, C2, C3, C4, C5, C6, C7, and C8 extending in a second direction D2 that intersects (e.g., is perpendicular to) the first direction D1. For example, semiconductor products SC11, SC12, SC13, SC14, SC15, SC16, SC17, and SC18 can form the first row R1, and semiconductor products SC11, SC21, SC31, SC41, SC51, SC61, SC71, and SC81 can form the first column C1. Rows R1 to R8 and columns C1 to C8 can be conceptually shown to explain the arrangement of semiconductor products SC11 to SC88, and can be arranged differently in test board 1100a.

[0060] In some example embodiments, test board 1100a may include a substrate and a plurality of sockets disposed on the substrate for securing a plurality of semiconductor products SC11 to SC88 to test board 1100a. For example, the substrate may have upper and lower surfaces opposite each other. For example, the substrate may be a printed circuit board (PCB). For example, the plurality of sockets may provide mechanical and electrical connections between the substrate and the plurality of semiconductor products SC11 to SC88, and may be formed in various ways. For example, the plurality of sockets may be slots, etc.

[0061] Reference Figure 3B , Figure 3C and Figure 3D It shows that it includes Figure 3A Examples of multiple test channels in the test board 1100a are shown, and examples of channel layout data CLDa, CLDb, and CLDc representing information associated with the configuration of the multiple test channels are shown.

[0062] In some example embodiments, such as Figure 3BAs shown, multiple test channels CH1a, CH2a, CH3a, CH4a, CH5a, CH6a, CH7a, CH8a, CH9a, CH10a, CH11a, CH12a, CH13a, CH14a, CH15a, and CH16a can be formed to receive test signals for testing corresponding semiconductor products arranged in rows along the channel layout data in the first direction D1 (e.g., in the row direction). Some of the semiconductor products SC11 to SC88 arranged in a row can share a test channel. For example, among the semiconductor products SC11 to SC18 arranged in the first row R1, semiconductor products SC11, SC12, SC13, and SC14 can be connected to test channel CH1a, and semiconductor products SC15, SC16, SC17, and SC18 can be connected to test channel CH9a.

[0063] In some example embodiments, such as Figure 3C As shown, multiple test channels CH1b, CH2b, CH3b, CH4b, CH5b, CH6b, CH7b, CH8b, CH9b, CH10b, CH11b, CH12b, CH13b, CH14b, CH15b, and CH16b can be formed to accommodate corresponding semiconductor products arranged in columns along the channel layout data in the second direction D2 (e.g., in the column direction). Some of the semiconductor products SC11 to SC88 arranged in the second direction D2 can share a test channel. For example, among the semiconductor products SC11 to SC81 arranged in the first column C1, semiconductor products SC11, SC21, SC31, and SC41 can be connected to test channel CH1b, and semiconductor products SC51, SC61, SC71, and SC81 can be connected to test channel CH9b.

[0064] In some example embodiments, such as Figure 3D As shown, multiple test channels CH1c, CH2c, CH3c, and CH4c can be formed to receive test signals used to test the corresponding semiconductor products. Some of the multiple semiconductor products SC11 to SC88 can share a single test channel. For example, semiconductor products SC11, SC12, SC13, SC14, SC15, SC16, SC17, SC18, SC21, SC22, SC23, SC24, SC31, SC32, SC33, and SC34 can be connected to test channel CH1c.

[0065] although Figure 3A , Figure 3B , Figure 3C and Figure 3DA specific number of semiconductor products and a specific number of test channels are shown, but the example embodiment is not limited thereto.

[0066] Figure 4A and Figure 4B It is shown that it includes Figure 2 A block diagram of an example of the first and second test modules in the test equipment.

[0067] Reference Figure 4A The first test module 1200a may include a test signal generation module 1210 and a first test result generation module 1220.

[0068] The test signal generation module 1210 can generate a test signal TS and provide the test signal TS to the test board 1100. For example, multiple semiconductor products SC can receive the test signal TS. As described above, the test board 1100 may include multiple test channels, and some semiconductor products can share a test channel. Therefore, semiconductor products sharing the same test channel can receive the test signal TS through the same test channel.

[0069] The first test result generation module 1220 can receive a test signal TS from the test signal generation module 1210 and can receive multiple first test result signals TRS1 from the test board 1100. For example, each of the multiple semiconductor products SC can generate and output a corresponding one of the multiple first test result signals TRS1 as the result of a first test operation performed in response to the test signal TS. The first test result generation module 1220 can perform a first test operation in response to the test signal TS to determine whether each of the multiple semiconductor products SC is normal or defective based on a corresponding one of the multiple first test result signals TRS1, and can generate a test chart TM representing the result of the first test operation. For example, the test chart TM may include information indicating whether each semiconductor product is normal or defective.

[0070] In some example embodiments, the test signal generation module 1210 and the first test result generation module 1220 can be implemented as a single integrated module. In other example embodiments, the test signal generation module 1210 and the first test result generation module 1220 can be implemented as separate and different modules.

[0071] refer to Figure 4B The second test module 1300a may include a test pattern division module 1310 and a second test result generation module 1320.

[0072] The test pattern partitioning module 1310 can receive the channel layout data (CLD) from the test board 1100. According to the reference... Figure 11A , Figure 11B and Figure 11C In the described example embodiment, the channel layout data CLD can be stored in various locations. The test pattern partitioning module 1310 can partition the test pattern TM into a first region and a second region based on the channel layout data CLD and a first test result from a first test operation, and can generate a region-partitioned test pattern TM'. The first region can identify semiconductor products among multiple semiconductor products that share the same test channel and have been determined to be completely defective, and the second region can represent semiconductor products other than those identified in the first region.

[0073] The second test result generation module 1320 can utilize information from the first and second regions, a first probability model PM1, and a second probability model PM2 (e.g., based on the region-divided test map TM', the first probability model PM1, and the second probability model PM2) to perform a second test operation to determine whether the defect in the semiconductor product identified in the first region is a board-related defect caused by characteristics of the test board 1100 or a defect in the semiconductor product itself, and can generate a second test result signal TRS2 representing the result of the second test operation. For example, the first probability model PM1 and the second probability model PM2 can be stored in the second test result generation module 1320.

[0074] In some example embodiments, the test graph partitioning module 1310 and the second test result generation module 1320 can be implemented as a single integrated module. In other example embodiments, the test graph partitioning module 1310 and the second test result generation module 1320 can be implemented as separate and distinct modules.

[0075] Figure 5 This is a block diagram illustrating a test apparatus according to an example embodiment.

[0076] Reference Figure 5 The test device 2000 includes a processor 2100, an input / output (I / O) device 2200, a network interface 2300, a random access memory (RAM) 2400, a read-only memory (ROM) 2500, and a storage device 2600. Figure 5 It shows Figure 2 All first test modules 1200 and second test modules 1300 are examples implemented in software. For ease of explanation, details related to... Figure 2 The components corresponding to test board 1100 in the test.

[0077] The test device 2000 can be a computing system. For example, the computing system can be a fixed computing system such as a desktop computer, workstation, or server, or a portable computing system such as a laptop computer.

[0078] Processor 2100 can be used to perform computational operations and / or calculations. For example, processor 2100 may include a core or processor core for executing any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit Extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, processor 2100 can access memory (e.g., RAM 2400 or ROM 2500) via a bus and can execute instructions stored in RAM 2400 or ROM 2500. Figure 5 As shown, RAM 2400 can store and Figure 2 The first test module 1200 and the second test module 1300 correspond to a program PR or at least some elements of a program PR, and the program PR can allow the processor 2100 to execute operations for testing semiconductor products using probabilistic model-based testing (e.g., Figure 1 (Operations S100, S200, S300, and S400). In some example embodiments, the processor 2100 may include multiple cores and / or may include a cache memory to enhance computing power.

[0079] Specifically, the program PR may include multiple instructions and / or procedures executable by the processor 2100, and the multiple instructions and / or procedures included in the program PR may allow the processor 2100 to perform operations for testing a semiconductor product using a probabilistic model-based test, according to the example embodiment. Each procedure may represent a series of instructions for performing a specific task. A procedure may be a function, routine, subroutine, or subroutine. Each program may process data provided from outside the test device 2000 and / or data generated by another program.

[0080] Storage device 2600 can store data for the operation of processor 2100 and test device 2000. For example, storage device 2600 can store a program PR. The program PR, or at least some elements thereof, can be loaded from storage device 2600 into RAM 2400 for execution by processor 2100. Storage device 2600 can store source files written in a programming language, and processor 2100 can generate the program PR by compiling the source files and load at least some portions of the program PR into RAM 2400.

[0081] Storage device 2600 can store data to be processed by processor 2100, or data obtained through processing by processor 2100. Processor 2100 can process the data stored in storage device 2600 based on program PR to generate new data, and can store the generated data in storage device 2600.

[0082] In some example embodiments, storage device 2600 may include any non-transitory computer-readable storage medium for providing commands and / or data to a computer. For example, non-transitory computer-readable storage media may include volatile memory such as static random access memory (SRAM), dynamic random access memory (DRAM), and non-volatile memory such as flash memory, magnetoresistive random access memory (MRAM), phase-change random access memory (PRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc. The non-transitory computer-readable storage medium may be inserted into a computer, integrated into a computer, or coupled to a computer via a communication medium such as a network and / or wireless link.

[0083] I / O device 2200 may include input devices such as a keyboard and a pointing device, and may also include output devices such as a display device and a printer. For example, a user can trigger the execution of program PR on processor 2100 through I / O device 2200, and can provide or check various inputs, outputs and / or data.

[0084] Network interface 2300 can provide access to networks outside of test equipment 2000. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of link. Various inputs can be provided to test equipment 2000 through network interface 2300, and various outputs can be provided to another computing system through network interface 2300.

[0085] In some example embodiments, the first test module 1200 and the second test module 1300 may be implemented as instructions or program code executable by the processor 2100. In some example embodiments, the processor 2100 may be configured to efficiently execute the instructions or program code included in the first test module 1200 and the second test module 1300.

[0086] although Figure 5 An example is shown that includes only one processor 2100 and one storage device 2600. For example, a first test module 1200 and a second test module 1300 share the processor 2100 and the storage device 2600, but the example embodiment is not limited thereto. For example, the test device 2000 may include separate processors and separate storage devices for the first test module 1200 and the second test module 1300.

[0087] Figure 6 Is to show execution Figure 1 The flowchart is an example of the second test operation.

[0088] refer to Figure 1and Figure 6 When the second test operation is performed (operation S400), the first conditional probability can be calculated based on the information of the first region and the second region and the first probability model (operation S410), and the second conditional probability can be calculated based on the information of the first region and the second region and the second probability model (operation S420).

[0089] In some example embodiments, the second test operation can be performed based on a likelihood ratio test. For example, the second test operation can be performed based on a probability comparison using Bayesian factors.

[0090] In statistics, the likelihood ratio test is a hypothesis test used to compare the goodness of fit between two competing statistical models based on their likelihood ratios. Typically, one competing model is obtained by maximizing the entire parameter space, while the other is obtained after imposing some constraints. In the likelihood ratio test, if the observed data support the more constrained model (e.g., the null hypothesis), the likelihoods of the two models may not be significantly different, and the difference will not exceed the value attributable to sampling error. That is, the difference between the likelihoods of the two models will not be significantly greater than the sampling error. Therefore, the likelihood ratio test can assess whether the ratio is significantly different from one, or equivalently, whether its natural logarithm is significantly different from zero.

[0091] In some example embodiments, the first probabilistic model can represent a model in which defects are globally and randomly distributed, not limited to any particular region. For example, the first probabilistic model can be obtained by simulating a scenario where defective semiconductor products identified as defective by a first test operation are randomly distributed across the entire area of ​​a test pattern, regardless of the first and second regions. For example, the first probabilistic model can correspond to the statistical model obtained by maximizing the likelihood over the full parameter space among the two competing statistical models described above.

[0092] In some example embodiments, the second probabilistic model can represent a model in which defects occur locally and deterministically in a specific region, for example, a model in which anomaly regions exist and defects occur deterministically in the anomaly regions. For example, the second probabilistic model can be obtained by simulating a situation where defective semiconductor products identified as defective by a first test operation are deterministically identified in a first region and randomly identified in a second region (i.e., the defective semiconductor products identified as defective by the first test operation are necessarily distributed in the first region and randomly distributed in the second region). For example, the second probabilistic model can correspond to a statistical model obtained after applying some constraints to the two competing statistical models described above.

[0093] In some example embodiments, each of the first and second probability models can be defined based on various probability variables and / or probability distributions. For example, each of the first and second probability models can be defined based on a probability mass function of a multivariate hypergeometric distribution, but the example embodiments are not limited thereto.

[0094] Subsequently, a second test result of the second test operation can be output based on the first conditional probability, the second conditional probability, and a predetermined threshold (operation S430). (Refer to...) Figure 7 Describe operation S430.

[0095] Figure 7 It is shown Figure 6 The flowchart shows an example of the output of the second test result of the second test operation.

[0096] Reference Figure 6 and Figure 7 The second test result of the second test operation (operation S430) can have a first value. The first value can be calculated by dividing the first conditional probability by the second conditional probability (operation S431). For example, the first value V1 can be obtained based on Equation 1.

[0097] [Equation 1]

[0098]

[0099] In equation 1, and This represents the first conditional probability obtained in operation S410 (e.g., the probability obtained under the first probability model PM1 with a global and randomly distributed defect), and and This represents the second conditional probability obtained during operation S420 (e.g., the probability obtained under the second probability model PM2 where the defect is deterministically located in the anomalous region). Additionally, the term "Dutmap" refers to the test map TM, and "AFC" refers to all fault channel regions, e.g., semiconductor products sharing the same test channel and already identified as a first region that is completely defective.

[0100] The first value is compared with a predetermined threshold, and when the first value is less than the predetermined threshold (operation S433: Yes), the defect in the semiconductor product identified in the first area can be determined as a board-related defect (operation S435). In this example, the semiconductor product identified in the first area can be preserved by retesting. For example, a different test board can be used to retest the semiconductor products included in the first area.

[0101] When the first value is greater than or equal to a predetermined threshold (operation S433: No), defects in the semiconductor products included in the first region can be determined as defects in the semiconductor products themselves, regardless of the characteristics of the test board. For example, it can be determined that the semiconductor products identified in the first region are inherently defective, regardless of the characteristics of the test board. In this example, defect analysis can be performed on the semiconductor products identified in the first region, or the semiconductor products identified in the first region can be considered defective and discarded.

[0102] In some example embodiments, each of the first value and the predetermined threshold can be a real number greater than 0 and less than 1. When the first value is close to 0, the second probability model gains stronger support, increasing the likelihood that the defect in the semiconductor product identified in the first region is a board-related defect. Conversely, when the first value is close to 1, the first probability model gains stronger support, increasing the likelihood that the defect in the semiconductor product included in the first region is not a board-related defect. Therefore, a predetermined real number between 0 and 1 can be set as the predetermined threshold.

[0103] However, the example embodiments are not limited thereto. For example, a logarithmic or similar function can be used to transform the first value into a second value, and the second value can be used instead of the first value. For example, the second value can indicate that the defect in the semiconductor product identified in the first region is a board-related defect when the first value and / or the second value is greater than a predetermined threshold, or indicate that the defect in the semiconductor product included in the first region is not a board-related defect when the first value and / or the second value is less than or equal to the predetermined threshold. Furthermore, the example embodiments can be varied and / or modified into various other forms.

[0104] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C and Figure 9D This is a diagram used to describe a method for testing a semiconductor product according to an example embodiment.

[0105] Reference Figure 8A , Figure 8B , Figure 8C and Figure 8D This shows that based on Figure 3A Test board 1100a and Figure 3B An example of performing the first and second test operations on the channel layout data of test channels CH1a to CH16a.

[0106] like Figure 8AAs shown, when the first test operation is performed, semiconductor products SC12, SC27, SC31, SC32, SC33, SC34, SC63, SC66, SC85, SC86, SC87, and SC88, among the multiple semiconductor products SC11 to SC88 included in test board 1100a-1, can be identified as defective. Figure 8A In the subsequent figures, semiconductor products identified as defective are indicated by shaded lines.

[0107] As a result of the first operation, such as Figure 8B As shown, multiple definite values ​​can be obtained, including V11a, V12a, V13a, V14a, V15a, V16a, V17a, V18a, V21a, V22a, V23a, V24a, V25a, V26a, V27a, V28a, V31a, V32a, V33a, V34a, V35a, V36a, V37a, V38a, V41a, V42a, V43a, V44a, V45a, V46a, V47a, and V4. Test chart TMa for V51a, V52a, V53a, V54a, V55a, V56a, V57a, V58a, V61a, V62a, V63a, V64a, V65a, V66a, V67a, V68a, V71a, V72a, V73a, V74a, V75a, V76a, V77a, V78a, V81a, V82a, V83a, V84a, V85a, V86a, V87a, and V88a. In Figure 8B In the subsequent figures, shaded lines illustrate the determination values ​​corresponding to semiconductor products identified as defective.

[0108] In some example embodiments, a defined value may correspond to a test result of a semiconductor product and may have different values ​​depending on whether the semiconductor product is determined to be normal or defective. For example, the defined value V11a corresponding to the test result of a semiconductor product SC11 that has been determined to be normal may have a first value (e.g., "0"). For example, the defined value V12a corresponding to the test result of a semiconductor product SC12 that has been determined to be defective may have a second value (e.g., "1") that is different from the first value. However, the example embodiments are not limited thereto.

[0109] After that, as Figure 8CAs shown, the test map TMa can be divided into a first region and a second region REG2a. The first region includes a first sub-region REG11a and a second sub-region REG12a, thereby generating a region-divided test map TMa'. For example, the first region may include a first sub-region REG11a and a second sub-region REG12a. The first sub-region REG11a may identify semiconductor products SC31, SC32, SC33, and SC34 that share test channel CH3a and have been identified as completely defective, and the second sub-region REG12a may identify semiconductor products SC85, SC86, SC87, and SC88 that share test channel CH16a and have been identified as completely defective. The second region REG2a may identify semiconductor products other than those identified in the first sub-regions REG11a and REG12a of the first region.

[0110] After that, as Figure 8D As shown, the reference model can be performed using the first probability model PM1 and the second probability model PM2. Figure 6 and Figure 7 The second test operation is described. For example, the test results of the second test operation using the first probability model PM1 are... Figure 8D The left-hand side of case 1a is conceptually shown, and the test results of the second test operation using the second probability model PM2 are presented in... Figure 8D The scenario on the right is conceptually illustrated in case 2a. A second operation can be performed by calculating the probabilities under the first probability model PM1 and the second probability model PM2 based on the test pattern TMA to obtain a first value, and comparing the first value with a predetermined threshold. Subsequently, when the first value is less than the predetermined threshold, it can be determined that the test pattern TMA supports the second probability model PM2 (e.g., the defects deterministically appear in the semiconductor products identified in the first regions REG11a and REG12a, and randomly appear in the second region REG2a), thus determining that the defects in semiconductor products SC31, SC32, SC33, SC34, SC85, SC86, SC87, and SC88 are board-related defects.

[0111] Reference Figure 9A , Figure 9B , Figure 9C and Figure 9D This shows that based on Figure 3A Test board 1100a and Figure 3B This section provides an example of performing the first and second test operations on the channel layout data of test channels CH1a to CH16a. For simplicity, details related to... Figure 8A , Figure 8B , Figure 8C and Figure 8D The description is repetitive or overlapping.

[0112] like Figure 9A As shown, when the first test operation is performed, semiconductor products SC12, SC14, SC15, SC16, SC21, SC22, SC24, SC25, SC27, SC28, SC31, SC32, SC33, SC34, SC41, SC43, SC45, SC47, SC53, SC54, SC56, SC61, SC62, SC63, SC66, SC67, SC68, SC72, ​​SC74, SC76, SC78, SC82, SC83, SC85, SC86, SC87, and SC88 among the multiple semiconductor products SC11 to SC88 included in test board 1100a-2 can be identified as defective.

[0113] Therefore, as Figure 9B As shown, multiple definite values ​​including V11b, V12b, V13b, V14b, V15b, V16b, V17b, V18b, V21b, V22b, V23b, V24b, V25b, V26b, V27b, V28b, V31b, V32b, V33b, V34b, V35b, V36b, V37b, V38b, V41b, V42b, V43b, V44b, V45b, V46b, V47b, can be obtained. Test plots TMb for 48b, V51b, V52b, V53b, V54b, V55b, V56b, V57b, V58b, V61b, V62b, V63b, V64b, V65b, V66b, V67b, V68b, V71b, V72b, V73b, V74b, V75b, V76b, V77b, V78b, V81b, V82b, V83b, V84b, V85b, V86b, V87b, and V88b.

[0114] After that, as Figure 9C As shown, the test map TMb can be divided into the first region REG11b and REG12b and the second region REG2b, and the test map TMb' with the region division can be obtained.

[0115] After that, as Figure 9D As shown, the reference model can be performed using the first probability model PM1 and the second probability model PM2. Figure 6 and Figure 7 The second test operation is described. For example, in Figure 9D The left-hand side of case 1b conceptually illustrates the test results of the second test operation using the first probability model PM1, and... Figure 9DThe test results of a second test operation using the second probability model PM2 are conceptually illustrated in case 2b on the right. The second operation can be performed by calculating the probabilities under the first probability model PM1 and the second probability model PM2 based on the test pattern TMb to obtain a first value and comparing the first value with a predetermined threshold. Subsequently, when the first value is greater than the predetermined threshold, it can be determined that the test pattern TMb supports the first probability model PM1 (e.g., defects occur randomly throughout the entire region of the first region REG11b and REG12b and the second region REG2b), and therefore it can be determined that the defects of semiconductor products SC31, SC32, SC33, SC34, SC85, SC86, SC87, and SC88 are not board-related defects (e.g., it can be determined that the defects of semiconductor products SC31, SC32, SC33, SC34, SC85, SC86, SC87, and SC88 are defects inherent to the semiconductor products themselves).

[0116] In some cases, even if the first regions REG11a and REG12a and the second region REG2a in test pattern TMa are substantially the same as the first regions REG11b and REG12b and the second region REG2b in test pattern TMb, the determination of whether the defects of semiconductor products SC31, SC32, SC33, SC34, SC85, SC86, SC87, and SC88 are board-related defects can differ depending on the defect distribution across the test pattern. For example, in test pattern TMa, the number of defective semiconductor products can be relatively small, and the defective semiconductor products can be concentrated only in the first regions REG11a and REG12a. Therefore, it can be determined that the defects of semiconductor products SC31, SC32, SC33, SC34, SC85, SC86, SC87, and SC88 are board-related defects with a high probability. Conversely, in the test pattern TMb, the number of defective semiconductor products may be relatively large, and the distribution of defective semiconductor products may not correspond to a specific spatial pattern. Therefore, it can be determined that the defects of semiconductor products SC31, SC32, SC33, SC34, SC85, SC86, SC87 and SC88 are highly probable to be board-related defects.

[0117] Although the example embodiments are described based on test patterns obtained using a specific number of semiconductor products and test channels with a specific structure, the example embodiments are not limited thereto.

[0118] In some example embodiments, even if operation S300 is performed, the test pattern may not include the first region, and the process can then be terminated without performing operation S400. For example, when the first region is not present in the test pattern, it can be determined that no board-related defects exist without performing operation S400.

[0119] Figure 10This is a flowchart illustrating a method for testing a semiconductor product according to an example embodiment. For the sake of brevity, details related to... Figure 1 The description is repetitive or overlapping.

[0120] Reference Figure 10 In the method for testing a semiconductor product according to the example embodiment, operations S100, S200, S300, and S400 can be compared with those of the reference embodiment. Figure 1 The operations described are basically the same.

[0121] Channel layout data for the test board can be received (operation S250). For example, channel layout data can be received inside the test equipment. For example, channel layout data can be received from an external device located outside the test equipment. For example, channel layout data can be received from the test board.

[0122] Figure 11A , Figure 11B and Figure 11C It is shown that it includes Figure 2 A block diagram of an example of the second test module in the test equipment. For the sake of brevity, [the following is omitted]. Figure 4B The description is repetitive or overlapping.

[0123] refer to Figure 11A The second test module 1300b may include a test pattern division module 1310 and a second test result generation module 1320, and may also include a memory 1330.

[0124] In addition to the memory 1330, the second test module 1300b can be connected with... Figure 4B The second test module 1300a is basically the same.

[0125] The memory 1330 can store channel layout data CLD. The test pattern partitioning module 1310 can operate in response to receiving the channel layout data CLD internally from the memory 1330.

[0126] although Figure 11A An example is shown where the memory 1330 for storing channel layout data CLD is included in the second test module 1300b, but the example embodiment is not limited thereto, and the memory 1330 may be located in other locations outside the second test module 1300b and inside the test equipment.

[0127] refer to Figure 11B The second test module 1300c may include a test pattern division module 1310 and a second test result generation module 1320.

[0128] The second test module 1300c and the test pattern division module 1310 can operate in response to receiving channel layout data (CLD) from the external device 1350. For example, the external device 1350 can be a device located outside the test equipment. For example, it can use... Figure 5 The I / O device 2200 and / or network interface 2300 in the middle receive the channel layout data CLD via wired and / or wireless communication.

[0129] refer to Figure 11C The second test module 1300d may include a test pattern partitioning module 1310 and a second test result generation module 1320.

[0130] With reference Figure 2 Depending on the description, test board 1100' may also include a memory MEM for storing channel layout data CLD. The second test module 1300d and the test pattern partitioning module 1310 may operate in response to receiving channel layout data CLD from test board 1100'.

[0131] Figure 12 This is a flowchart illustrating a method for testing a semiconductor product according to an example embodiment. For the sake of brevity, details related to... Figure 1 The description is repetitive or overlapping.

[0132] Reference Figure 12 In a method for testing semiconductor products according to an example embodiment, a first test operation is performed using multiple test boards to determine whether each semiconductor product is normal or defective (operation S1100). Multiple semiconductor products are mounted on each of the multiple test boards. Multiple test patterns representing the results of the first test operation are generated (operation S1200). Based on at least one channel layout data of the multiple test boards, each of the multiple test patterns is divided into a first region and a second region (operation S1300). The first region may identify semiconductor products sharing the same test channel and already determined to be completely defective, and the second region may identify semiconductor products other than those identified in the first region. Using information from the first and second regions, a first probability model, and a second probability model, a second test operation is performed to determine whether the defects in the semiconductor products included in the first region are board-related defects caused by characteristics of each of the multiple test boards (operation S1400). In addition to using multiple test boards and multiple test patterns, operations S1100, S1200, S1300, and S1400 can be respectively combined with… Figure 1 Operations S100, S200, S300, and S400 are essentially the same. In some example embodiments, further operations can be performed similar to... Figure 10 The operation S250 corresponds to the operation of receiving channel layout data for each test board.

[0133] In some example embodiments, first test operations and second test operations on multiple test boards can be performed sequentially. In some example embodiments, first test operations and second test operations on at least some of the multiple test boards can be performed substantially simultaneously or concurrently.

[0134] Figure 13 This is a block diagram illustrating a test apparatus according to an example embodiment. For the sake of brevity, symbols and symbols are omitted. Figure 2 The description is repetitive or overlapping.

[0135] Reference Figure 13 The test equipment 1000a includes multiple test boards 1102, 1104 and 1106, a first test module 1200 and a second test module 1300.

[0136] In addition to the test equipment 1000a including multiple test boards 1102, 1104, and 1106, the test equipment 1000a can be used with... Figure 2 The testing equipment is basically the same as 1000. Each of the multiple test boards 1102, 1104, and 1106 can be used with... Figure 2 The test board 1100 is basically the same.

[0137] In some example embodiments, the multiple test boards 1102, 1104 and 1106 may be attachable and removable.

[0138] In some example embodiments, test equipment 1000a may be equipped with one test board at a time, and multiple test boards 1102, 1104, and 1106 may be tested sequentially. For example, test board 1102 may be attached to test equipment 1000a, and a first test operation and a second test operation may be performed on the semiconductor product SC included in test board 1102. After completing the first and second test operations on test board 1102, test board 1102 may be detached from test equipment 1000a, and test board 1104 may be attached to test equipment 1000a, and a first and second test operation may be performed on the semiconductor product SC included in test board 1104.

[0139] In some example embodiments, test equipment 1000a may be equipped with two or more test boards at a time, and at least some of the test boards 1102, 1104, and 1106 may be performed substantially simultaneously. For example, test boards 1102 and 1104 may be attached to test equipment 1000a simultaneously, and a first test operation and a second test operation may be performed simultaneously on the semiconductor product SC included in test boards 1102 and 1104.

[0140] In some example embodiments, multiple test boards 1102, 1104, and 1106 may all have the same structure and the same type. In this example, when testing the initially attached test board, channel layout data corresponding to that test board can be received once, and when testing other test boards subsequently, the operation of receiving channel layout data can be omitted.

[0141] In some example embodiments, at least some of the multiple test boards 1102, 1104, and 1106 may have different structures and different types. In this example, whenever the structure and type of the attached test board changes, channel layout data corresponding to the test board can be received.

[0142] As those skilled in the art will understand, exemplary embodiments may be embodied as systems, methods, computer program products, and / or computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon. The computer-readable program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be any tangible medium that may contain or store a program used by or in connection with an instruction execution system, apparatus, or device. For example, a computer-readable medium may be a non-transitory computer-readable medium.

[0143] Figure 14A and Figure 14B This is a block diagram illustrating an example of a semiconductor product according to an example embodiment.

[0144] Reference Figure 14A The illustration shows an example of a semiconductor product provided in the form of a semiconductor chip, and an example of a semiconductor chip being a memory (or memory chip). For example, memory 200 could be one of various volatile memories such as DRAM.

[0145] The memory 200 may include control logic 210, refresh control circuit 215, address register 220, bank control logic 230, row address multiplexer 240, column address latch 250, row decoder, column decoder, memory cell array, sense amplifier unit, input / output (I / O) gate circuit 290, data I / O buffer 295 and data I / O pads 299.

[0146] The memory cell array may include multiple memory cells. The memory cell array may include multiple memory bank arrays, such as first to fourth memory bank arrays 280a, 280b, 280c, and 280d. The row decoder may include multiple memory bank row decoders, such as first to fourth memory bank row decoders 260a, 260b, 260c, and 260d connected to the first to fourth memory bank arrays 280a, 280b, 280c, and 280d, respectively. The column decoder may include multiple memory bank column decoders, such as first to fourth memory bank column decoders 270a, 270b, 270c, and 270d connected to the first to fourth memory bank arrays 280a, 280b, 280c, and 280d, respectively. The sensing amplifier unit may include multiple memory bank sensing amplifiers, such as first to fourth memory bank sensing amplifiers 285a, 285b, 285c and 285d respectively connected to the first to fourth memory bank arrays 280a, 280b, 280c and 280d.

[0147] The first memory array 280a to the fourth memory array 280d, the first memory row decoder 260a to the fourth memory row decoder 260d, the first memory column decoder 270a to the fourth memory column decoder 270d, and the first memory sensing amplifier 285a to the fourth memory sensing amplifier 285d can respectively form the first memory to the fourth memory. For example, a first memory array 280a, a first memory row decoder 260a, a first memory column decoder 270a, and a first memory sensing amplifier 285a can form a first memory; a second memory array 280b, a second memory row decoder 260b, a second memory column decoder 270b, and a second memory sensing amplifier 285b can form a second memory; a third memory array 280c, a third memory row decoder 260c, a third memory column decoder 270c, and a third memory sensing amplifier 285c can form a third memory; and a fourth memory array 280d, a fourth memory row decoder 260d, a fourth memory column decoder 270d, and a fourth memory sensing amplifier 285d can form a fourth memory.

[0148] Address register 220 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from a controller located outside memory 200. Address register 220 can provide the received bank address BANK_ADDR to bank control logic 230, the received row address ROW_ADDR to row address multiplexer 240, and the received column address COL_ADDR to column address latch 250.

[0149] The memory bank control logic 230 can generate a memory bank control signal in response to the receipt of the memory bank address BANK_ADDR. One of the first to fourth memory bank row decoders 260a to 260d corresponding to the received memory bank address BANK_ADDR can be activated in response to the memory bank control signal generated by the memory bank control logic 230, and one of the first to fourth memory bank column decoders 270a to 270d corresponding to the received memory bank address BANK_ADDR can be activated in response to the memory bank control signal generated by the memory bank control logic 230.

[0150] The refresh control circuit 215 can generate a refresh address REF_ADDR in response to the receipt of a refresh command or the entry of any self-refresh mode. For example, the refresh control circuit 215 may include a refresh counter configured to sequentially change the refresh address REF_ADDR from the first address of the memory cell array to the last address of the memory cell array. The refresh control circuit 215 may receive control signals from the control logic 210.

[0151] Row address multiplexer 240 can receive row address ROW_ADDR from address register 220 and refresh address REF_ADDR from refresh control circuitry 215. Row address multiplexer 240 can selectively output row address ROW_ADDR or refresh address REF_ADDR. The row address output from row address multiplexer 240 (e.g., row address ROW_ADDR or refresh address REF_ADDR) can be applied to first bank row decoders 260a through fourth bank row decoders 260d.

[0152] One of the first to fourth bank row decoders 260a to 260d is activated to decode the row address output from the row address multiplexer 240 and to activate the word line corresponding to that row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to that row address.

[0153] Column address latch 250 can receive column address COL_ADDR from address register 220 and can temporarily store the received column address COL_ADDR. Column address latch 250 can apply the temporarily stored or received column address COL_ADDR to the first memory bank column decoder 270a to the fourth memory bank column decoder 270d.

[0154] One of the first bank column decoders 270a to the fourth bank column decoder 270d is activated to decode the column address COL_ADDR output from the column address latch 250 and can control the I / O gate circuit 290 to output data corresponding to the column address COL_ADDR.

[0155] I / O gating circuit 290 may include circuitry for gating I / O data. For example, although not shown, I / O gating circuit 290 may include input data masking logic, a read data latch for storing data output from the first memory array 280a to the fourth memory array 280d, and a write driver for writing data to the first memory array 280a to the fourth memory array 280d.

[0156] Data DQ read from one of the first to fourth memory arrays 280a to 280d can be sensed by a sense amplifier coupled to that memory array and stored in a read data latch. The data DQ stored in the read data latch can be provided to the controller via data I / O buffer 295 and data I / O pads 299. Data DQ to be written to one of the first to fourth memory arrays 280a to 280d, received via data I / O pads 299, can be provided from the controller to data I / O buffer 295. Data DQ received via data I / O pads 299 and provided to data I / O buffer 295 can be written to a memory array via a write driver in I / O gating circuit 290.

[0157] Control logic 210 can control the operation of memory 200. For example, control logic 210 can generate control signals for memory 200 to perform data write operations or data read operations. Control logic 210 may include a command decoder 211 for decoding commands (CMD) received from the controller and a mode register 212 for setting the operating mode of memory 200.

[0158] Reference Figure 14B The illustration shows an example of a semiconductor product provided in the form of a semiconductor chip, and an example of a semiconductor chip being a memory (or memory chip). For example, memory 300 could be one of various non-volatile memories such as NAND flash memory.

[0159] The memory 300 may include a memory cell array 310, an address decoder 320, a page buffer circuit 330, a data input / output (I / O) circuit 340, a voltage generator 350, and a control circuit 360.

[0160] The memory cell array 310 can be connected to the address decoder 320 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The memory cell array 310 can also be connected to the page buffer circuit 330 via multiple bit lines (BL). The memory cell array 310 may include multiple memory cells (e.g., multiple non-volatile memory cells) connected to the multiple word lines (WL) and multiple bit lines (BL). The memory cell array 310 can be divided into multiple memory blocks BLK1, BLK2, ..., BLKz, each memory block comprising memory cells.

[0161] In some example embodiments, multiple memory cells may be arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure. A three-dimensional vertical array structure may comprise vertically oriented strings of cells such that at least one memory cell is positioned above another memory cell. At least one memory cell may include a charge trapping layer. Suitable configurations for memory cell arrays comprising 3D vertical array structures are described by reference in their entirety in the following patent documents: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0162] The control circuit 360 can receive commands CMD and addresses ADDR from a controller located outside the memory 300, and can control the erase, programming, and read operations of the memory 300 based on the commands CMD and addresses ADDR. The erase operation may include a sequence of erase cycles, and the programming operation may include a sequence of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. The read operation may include a normal read operation and a data recovery read operation.

[0163] For example, control circuit 360 can generate control signal CON for controlling voltage generator 350 based on command CMD, and can generate control signal PBC for controlling page buffer circuit 330, and can generate row address R_ADDR and column address C_ADDR based on address ADDR. Control circuit 360 can provide row address R_ADDR to address decoder 320, and can provide column address C_ADDR to data I / O circuit 340.

[0164] Address decoder 320 can be connected to memory cell array 310 via multiple string select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). For example, in a data erase / write / read operation, address decoder 320 can determine at least one of the multiple word lines (WL) as the selected word line, at least one of the multiple string select lines (SSL) as the selected string select line, and at least one of the multiple ground select lines (GSL) as the selected ground select line based on the row address R_ADDR.

[0165] Voltage generator 350 can generate voltage VS for the operation of memory 300 based on power PWR and control signal CON. Voltage VS can be applied to multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL via address decoder 320. In addition, voltage generator 350 can generate erase voltage VERS for erase operation based on power PWR and control signal CON.

[0166] Page buffer circuit 330 can be connected to memory cell array 310 via multiple bit lines BL. Page buffer circuit 330 may include multiple page buffers. Page buffer circuit 330 can store data DAT to be programmed into memory cell array 310, or can read data DAT sensed from memory cell array 310. In other words, page buffer circuit 330 can operate as a write driver or a sense amplifier depending on the operating mode of memory 300.

[0167] Data I / O circuit 340 can be connected to page buffer circuit 330 via data line DL. Based on column address C_ADDR, data I / O circuit 340 can provide data DAT from outside memory 300 to memory cell array 310 via page buffer circuit 330, or it can provide data DAT from memory cell array 310 to outside memory 300.

[0168] Although the semiconductor product described according to the example embodiment is based on DRAM and NAND flash memory, the semiconductor product according to the example embodiment may be or includes any volatile memory and / or any non-volatile memory, such as static random access memory (SRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), etc.

[0169] Figure 15A and Figure 15B This is a diagram illustrating an example of a semiconductor product according to an example embodiment.

[0170] Reference Figure 15A and Figure 15BThis illustrates an example of providing semiconductor products in the form of a semiconductor package that includes a semiconductor chip.

[0171] For example, such as Figure 15A As shown, the semiconductor package 700 may include a substrate 710 and a plurality of semiconductor chips CHP1, CHP2 and CHP3 stacked on the substrate 710. For example, each of the semiconductor chips CHP1 to CHP3 may be a memory chip, and the semiconductor package 700 may be a memory package.

[0172] In some example embodiments, semiconductor chips CHP1 to CHP3 can be stacked on substrate 710 with the surface where I / O pads are formed facing upwards. In some example embodiments, for each of semiconductor chips CHP1 to CHP3, the I / O pads can be arranged near one side of the semiconductor substrate. Thus, semiconductor chips CHP1 to CHP3 can be stacked in a stepped or stepped manner, allowing the I / O pads of each semiconductor chip to be exposed. In this stacked configuration, semiconductor chips CHP1 to CHP3 can be electrically connected to substrate 710 via bonding wires BW.

[0173] The stacked semiconductor chips CHP1 to CHP3 and multiple bonding lines BW can be secured by a sealing member 740, and an adhesive member 730 can be positioned between the substrate 710 and the semiconductor chips CHP1 to CHP3. Conductive bumps 720 can be formed on the bottom surface of the substrate 710 for electrical connection to external devices.

[0174] For example, such as Figure 15B As shown, the semiconductor package 800 may include a substrate 810 and a plurality of semiconductor chips CHP1, CHP2, and CHP3 stacked on the substrate 810. For simplicity, the details of the semiconductor package will be omitted. Figure 15A The description is repetitive or overlapping.

[0175] Each of the semiconductor chips CHP1 to CHP3 may further include a through-silicon via (TSV) 830. Conductive bumps 820 and sealing members 850 may be respectively connected to… Figure 15A The conductive bump 720 and the sealing member 740 are essentially the same.

[0176] In some example embodiments, for each of the semiconductor chips CHP1 to CHP3, the TSV 830 can be arranged at the same location in each semiconductor chip. Thus, the semiconductor chips CHP1 to CHP3 can be stacked such that the TSV 830 of each semiconductor chip can be completely overlapped (e.g., the arrangement of the TSV 830 can be perfectly matched in the semiconductor chips CHP1 to CHP3). In this stacked state, the semiconductor chips CHP1 to CHP3 can be electrically connected to each other and to the substrate 810 via the TSV 830 and the conductive material 840.

[0177] Although the example embodiments are described as providing semiconductor products in the form of semiconductor chips and / or semiconductor packages, the example embodiments are not limited thereto. For example, semiconductor products may be provided in the form of solution products, such as solid-state drives (SSDs), universal flash memory (UFS), multimedia cards (MMCs), embedded MMCs (eMMCs), secure digital cards (SDs), microSD cards, memory sticks, chip cards, universal serial bus (USB) cards, smart cards, compact flash memory (CF) cards, etc.

[0178] Figure 16 This is a flowchart illustrating a method for producing a semiconductor product according to an example embodiment.

[0179] Reference Figure 16 In the method for manufacturing semiconductor products according to the example embodiment, multiple semiconductor products are manufactured (operation S2100). For example, multiple wafers can be manufactured using semiconductor processes such as oxidation, photolithography, etching, deposition, ion implantation, and metal wiring, with each wafer comprising multiple semiconductor products. Subsequently, multiple semiconductor products can be manufactured or produced using assembly processes, packaging processes, etc.

[0180] Test multiple semiconductor products (operation S2200). For example, this can be based on a reference. Figures 1 to 13 The described example embodiment uses a probabilistic model-based test to perform operation S2200. For example, a test pattern can be obtained by performing a first test operation on each of a plurality of semiconductor products using a test board with a channel-sharing structure. The test pattern can be divided into a first region and a second region using the channel layout data of the test board. A second test operation can be performed using the divided regions and a predefined probabilistic model to determine whether each defective semiconductor product determined to be defective by the first test operation has a board-related defect.

[0181] The example embodiments can be applied to a wide variety of electronic devices and systems, including semiconductor products. For example, the example embodiments can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, and the like.

[0182] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments defined in the claims. Consequently, it should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting oneself to the specific exemplary embodiments disclosed, and modifications to the disclosed and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A method for testing semiconductor products, the method comprising: A first test operation is performed on a plurality of semiconductor products mounted on a test board to determine whether each of the plurality of semiconductor products is normal or defective, the test board including a plurality of test channels configured to receive test signals, and two or more semiconductor products sharing a single test channel among the plurality of test channels; A test graph is generated based on the first result of the first test operation; Based on the channel layout data of the test board, the test diagram is divided into a first region and a second region. The first region identifies semiconductor products that share the same test channel and have been determined to be completely defective, and the second region identifies semiconductor products other than those identified in the first region. and Using the information from the first and second regions, the first probability model, and the second probability model, a second test operation is performed to determine whether the defects of the semiconductor product identified in the first region are board-related defects caused by the characteristics of the test board.

2. The method according to claim 1, wherein, The second test operation is performed based on the likelihood ratio test.

3. The method according to claim 2, wherein, The first probability model is obtained by simulating a situation where defective semiconductor products identified as defective during the first test operation are randomly distributed on the test map including the first region and the second region, and the second probability model is obtained by simulating a situation where defective semiconductor products identified as defective during the first test operation are deterministically distributed in the first region and randomly distributed in the second region.

4. The method according to claim 3, wherein, Performing the second test operation includes: The first conditional probability is calculated based on the information from the first region and the second region, as well as the first probability model. The second conditional probability is calculated based on the information from the first and second regions and the second probability model; and The second test result of the second test operation is output using the first conditional probability, the second conditional probability, and the predetermined threshold.

5. The method according to claim 4, wherein, The second test result of the second test operation includes: The first value is calculated by dividing the first conditional probability by the second conditional probability; and The first value is compared with the predetermined threshold, and when the first value is less than the predetermined threshold, the defect of the semiconductor product identified in the first region is determined to be a board-related defect, and when the first value is greater than or equal to the predetermined threshold, the defect of the semiconductor product identified in the first region is determined not to be a board-related defect.

6. The method according to claim 5, wherein, When it is determined that the defect of the semiconductor product identified in the first area is a board-related defect, the semiconductor product identified in the first area is retested using a different test board.

7. The method according to claim 5, wherein, Each of the first value and the predetermined threshold is a real number greater than 0 and less than 1.

8. The method according to claim 7, wherein, As the first value approaches 0, the likelihood that the defect in the semiconductor product identified in the first region is a board-related defect increases, and as the first value approaches 1, the likelihood that the defect in the semiconductor product included in the first region is not a board-related defect increases.

9. The method according to claim 1, wherein, The first test operation and the second test operation are performed by a test device on which the test board is mounted.

10. The method according to claim 9, wherein, The first test operation and the second test operation are performed using the channel layout data stored in the test equipment.

11. The method according to claim 9, wherein, The first test operation and the second test operation are performed using the channel layout data from an external device located outside the test equipment.

12. The method according to claim 9, wherein, The first test operation and the second test operation are performed using the channel layout data stored in the test board.

13. A testing device, comprising: A test board includes multiple test channels for testing multiple semiconductor products mounted on the test board, each of the multiple test channels being configured to receive a test signal, and two or more semiconductor products sharing one of the multiple test channels; A first test module is configured to perform a first test operation to determine whether each of the plurality of semiconductor products is normal or defective, and to generate a test graph representing the result of the first test operation. and The second test module is configured to divide the test pattern into a first region and a second region based on the channel layout data of the test board, and to perform a second test operation using information from the first region and the second region, a first probability model and a second probability model to determine whether the defects of the semiconductor products included in the first region are board-related defects caused by the characteristics of the test board. The first region identifies semiconductor products that share the same test channel and have been identified as completely defective, and the second region identifies semiconductor products other than those identified in the first region.

14. The testing equipment according to claim 13, wherein, The second test module includes: At least one processor; and A non-transitory computer-readable medium configured to store program code executable by the at least one processor. Wherein, the at least one processor is configured to execute the program code as follows: The test map is divided into a first region and a second region; and Perform the second test operation.

15. The test apparatus of claim 13, further comprising a memory configured to store the channel layout data, wherein, The second test module is configured to receive the channel layout data from the memory and perform the second test operation based on the channel layout data.

16. The testing apparatus according to claim 13, wherein, The second test module is configured to receive the channel layout data from an external device located outside the test equipment, and to perform the second test operation based on the channel layout data.

17. The testing apparatus according to claim 13, wherein, The test board further includes a memory configured to store the channel layout data, and the second test module is configured to receive the channel layout data from the test board and perform the second test operation based on the channel layout data.

18. The test apparatus of claim 13, further comprising a test board connector configured to install and remove the test board.

19. A method for producing a semiconductor product, the method comprising: Manufacturing multiple semiconductor products; and The plurality of semiconductor products mounted on a test board are tested using test equipment. The test board includes multiple test channels for receiving test signals, wherein two or more semiconductor products share one of the multiple test channels. The testing of the plurality of semiconductor products includes: Perform a first test operation to determine whether each of the plurality of semiconductor products mounted on the test board is normal or defective; Generate a test graph representing the result of the first test operation; Based on the channel layout data of the test board, the test pattern is divided into a first region and a second region. The first region identifies semiconductor products that share the same test channels and have been determined to be completely defective. The second region identifies semiconductor products other than those identified in the first region. Using the information from the first and second regions, the first probability model, and the second probability model, a second test operation is performed to determine whether the defects of the semiconductor product identified in the first region are board-related defects caused by the characteristics of the test board.

20. The method according to claim 19, wherein, After completing the first test operation and the second test operation on the plurality of semiconductor products on the test board, the test board is removed from the test equipment, a second test board on which a plurality of second semiconductor products are mounted is attached to the test equipment, and the first test operation and the second test operation on the plurality of second semiconductor products are performed.

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