Data processing method for multi-chip and multi-chip

Abstract

The application provides a data processing method for a multi-grain chip and the multi-grain chip, and relates to the chip technical field.The method comprises the following steps: firstly, in response to a computing core of a first grain, a memory access transaction is initiated to a target storage controller of a second grain, and a shared attribute identifier is determined.Then, when the shared attribute identifier indicates that the memory access data is non-shared data, a shunting processing procedure is executed: if it is a write transaction, write request data is split into a control packet and a first data packet, the control packet is sent to the target storage controller through a home agent node, and after a write response is received, the first data packet is sent to the target storage controller through a data path bypassing the home agent node; if it is a read transaction, read request data is sent to the target storage controller through the home agent node, and a second data packet returned by the target storage controller through a data path bypassing the home agent node and a read response returned through the home agent node are received.The scheme can reduce the serialization processing overhead of cross-grain memory access in the multi-grain chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more specifically, to a data processing method for a polycrystalline chip and a polycrystalline chip. Background Technology

[0002] As Moore's Law reaches its limits, the area of ​​a single die is constrained by the size of the photolithography mask and cannot be increased indefinitely. Therefore, multi-die chips have become the mainstream technology. A multi-die chip refers to a chip architecture that interconnects multiple functionally independent dies through a die-to-die interface (D2D interface). To maintain cache consistency across dies, each die has a Home Node Function (HNF) as a serialization point for cross-die memory access transactions, responsible for listening and filtering, directory lookups, and transaction serialization.

[0003] In the existing scheme, when the computing core of the first die initiates a cross-die memory access to the storage controller of the second die, the data sequentially passes through the home proxy node of the first die, the inter-die interface, and the home proxy node of the second die before reaching the target storage controller; the returned data also returns along the same path. In this path, each cross-die memory access requires passing through the home proxy node twice, and the home proxy node needs to allocate a data buffer for each data packet and perform a status query, resulting in limited resource capacity. Under multi-transaction concurrency, the home proxy node is prone to becoming a bottleneck, with queuing delays occurring during data packet enqueueing and dequeueing, significantly increasing memory access latency.

[0004] Therefore, how to reduce the serialization processing overhead of cross-die memory access in multi-die chips, so as to reduce the resource occupation of home agent nodes and shorten memory access latency, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The purpose of this application is to provide a data processing method for multi-die chips and a multi-die chip, which can reduce the serialization processing overhead of cross-die memory access in multi-die chips, thereby reducing the resource occupation of home agent nodes and shortening memory access latency.

[0006] This application is implemented as follows: In a first aspect, this application provides a data processing method for a multi-chip chip, comprising the following steps: responding to a computing core of a first chip initiating a memory access transaction to a target memory controller of a second chip, and determining a shared attribute identifier; when the shared attribute identifier indicates that the memory access data in the memory access transaction is non-shared data, executing a splitting processing procedure. The splitting processing procedure includes: if the memory access transaction is a write transaction, splitting the write request data of the write transaction into a control packet and a first data packet, sending the control packet to the target memory controller via a home proxy node, and after receiving a write response returned by the target memory controller via the home proxy node, sending the first data packet to the target memory controller via a data path bypassing the home proxy node; if the memory access transaction is a read transaction, sending the read request data of the read transaction to the target memory controller via the home proxy node, and receiving a second data packet returned by the target memory controller based on the received read request data via a data path bypassing the home proxy node, and a read response returned by the home proxy node.

[0007] In some implementations, the steps for determining the shared attribute identifier include: the computing core of the first die sends the memory access request data corresponding to the memory access transaction to the home proxy node of the first die, and the home proxy node of the first die performs access heat analysis on the address range of the memory access request data according to a preset memory access attribute prediction mechanism to generate the shared attribute identifier.

[0008] In some implementations, the step of performing access heat analysis on the address ranges of memory access request data to generate shared attribute identifiers includes: the home proxy node of the first die monitors the source of memory access request data for each address range. When all memory access request data received by any address range within a preset time period comes from the computing core of the same die, the shared attribute identifier for subsequent memory access request data for that address range is set to a first value indicating non-sharing; otherwise, the shared attribute identifier is set to a second value indicating possible sharing.

[0009] In some implementations, the write request data includes payload data, a shared attribute identifier, and the node identifier of the target storage controller; the control packet carries the shared attribute identifier and the node identifier of the target storage controller, and the first data packet carries the payload data. The step of sending the control packet to the target storage controller via the home proxy node includes: the computing core of the first die sequentially sends the control packet to the target storage controller of the second die via the home proxy node of the first die, the inter-die interface, and the home proxy node of the second die. The step of sending the first data packet to the target storage controller via a data path bypassing the home proxy node after receiving the write response from the target storage controller via the home proxy node includes: the computing core of the first die responds to the received write response by sending the first data packet directly to the target storage controller via the inter-die interface; wherein, the write response is information fed back from the target storage controller to the computing core of the first die in response to the received control packet, sequentially via the home proxy node of the second die, the inter-die interface, and the home proxy node of the first die.

[0010] In some implementations, the second data packet carries the data requested by the read request data. The step of sending the read request data of a read transaction to the target storage controller via the home agent node includes: the first die's compute core sending the read request data sequentially via the first die's home agent node, the inter-die interface, and the second die's home agent node to the target storage controller of the second die. The step of receiving the second data packet returned by the target storage controller based on the received read request data via a data path bypassing the home agent node, and the read response returned via the home agent node, includes: the first die's compute core receiving the second data packet, which is data sent directly to the first die's compute core via the inter-die interface when the target storage controller determines that the read transaction is a non-shared data access based on the received read request data; the first die's home agent receiving the read response, which is information fed back to the first die's compute core by the target storage controller based on the received read request data via the second die's home agent node, the inter-die interface, and the first die's home agent node.

[0011] In some implementations, the read response is used to release the tracker resources that are pending in the home agent node of the first die and the home agent node of the second die.

[0012] In some implementations, the on-chip network of a multi-chip chip includes a first virtual channel located on a first die and a second virtual channel located on a second die. Sending a first data packet to the target storage controller via a data path bypassing the home proxy node includes: sending the first data packet to the target storage controller sequentially via the first virtual channel and the second virtual channel; receiving a second data packet returned by the target storage controller via the data path bypassing the home proxy node includes: receiving the second data packet returned sequentially via the second virtual channel and the first virtual channel.

[0013] In some implementations, the dies in a multi-die chip are interconnected through an inter-die interface. The inter-die interface includes an inter-die interface controller disposed on each die and a micro-bump physical link connecting each inter-die interface controller. The data path that bypasses the home agent node is a path for data transmission directly through the inter-die interface. When the data is transmitted through the inter-die interface, it is transmitted across dies after protocol conversion by the inter-die interface controller through the micro-bump physical link.

[0014] In some implementations, the shared attribute identifier includes a first value and a second value. The first value indicates that the accessed memory data is non-shared data, triggering a traffic splitting process; the second value indicates that the accessed memory data is potentially shared data, triggering a regular processing process. The regular processing process includes: if the memory access transaction is a write transaction, the write request data is sent to the target storage controller via the home agent node; and after receiving the write response returned by the target storage controller via the home agent node, the data requested to be written in the write request data is sent to the target storage controller via the home agent node; if the memory access transaction is a read transaction, the read request data is sent to the target storage controller via the home agent node, and the target storage controller returns the data requested to be read and the corresponding read response, based on the received read request data, via the home agent node.

[0015] In some implementations, the target storage controller includes a data buffer; when the memory access transaction is a write transaction and the shared attribute identifier indicates non-shared data, the target storage controller receives the first data packet and directly writes the payload data carried by the first data packet into the data buffer without going through a consistency status query.

[0016] In a second aspect, this application provides a multi-chip chip comprising a plurality of chips, each chip comprising at least one computing core, at least one home agent node, an on-chip network, at least one memory controller, and an inter-chip interface for connecting with other chips; wherein the computing core is used to implement the data processing method as described in any one of the first aspects above.

[0017] Compared with the prior art, this application has at least the following advantages or beneficial effects: In the data processing method for multi-die chips of this application, a shared attribute identifier is introduced to distinguish whether the accessed memory data is non-shared data. Based on this identifier, the data payload in a write or read transaction is stripped from the serial path of the home agent node, allowing it to bypass the home agent node and be transmitted directly. Thus, the payload of non-shared data no longer needs to pass through the home agent node at least twice and occupy its data buffer resources, as in existing technologies. This reduces queuing latency, shortens cross-die memory access latency, and frees up the processing capacity of the home agent node to serve other shared data accesses.

[0018] Specifically, in the scheme of this application, the payload of non-shared data no longer passes through the home agent node and no longer occupies the data buffer resources of the home agent node, thereby releasing the processing capacity of the home agent node and alleviating the funnel effect of the home agent node under high load. At the same time, the first and second data packets bypass the enqueue and dequeue processes of the home agent node, avoiding queuing delays and thus shortening the overall latency of cross-chip memory access. In addition, by separating the data payload from the control flow, this application can achieve routing separation of data flow and control flow, thereby avoiding the situation in traditional architectures where data must accompany state packets through all consistency nodes, effectively reducing the physical path length of data backhaul and further shortening latency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A typical path diagram for an existing write request process; Figure 2 This is a typical path diagram of an existing read request process; Figure 3 This is a flowchart of an embodiment of a data processing method for a multi-chip chip according to this application; Figure 4 This is a schematic diagram of the write request process in one embodiment of this application; Figure 5 This is a schematic diagram of the read request process in one embodiment of this application; Figure 6 This is a schematic diagram of the structure of a polycrystalline chip in one embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0022] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0023] First, it should be noted that, for ease of description, the following description uses a two-die multi-die chip (whether describing existing solutions or the solution of this application), and these two dies are referred to as the first die and the second die, respectively. However, it is understood that the principle is similar for multi-die chips with more dies (e.g., eight dies). That is, when the computing core of any die initiates a memory access transaction to the target memory controller of the other die, the principle and logic are the same.

[0024] In existing large multi-chip chips, on-chip networks with mesh or toroidal topologies are typically used to connect the various components. In terms of hardware configuration, the first and second chips are interconnected through a high-speed inter-chip interface. Each chip contains: a computing core, a home agent node, an on-chip network (responsible for routing to the appropriate target node based on the target node information in the request, data, or response), and a storage controller (typically connected to Double Data Rate (DDR) memory).

[0025] like Figure 1 As shown, the typical path of an existing write request process includes write allocation and data advance steps.

[0026] (1) The write allocation steps include: the computing core of the first die initiates a write request, which must first obtain ownership of the cache line, which involves the listening operation of multi-level home agent nodes.

[0027] (2) The data propulsion steps include: when performing Direct Write-Through (DWT) or Dirty Write, the data flow follows the path of the computing core of the first die, the home agent node of the first die, the inter-die interface of the first die, the inter-die interface of the second die, the home agent node of the second die, and the storage controller of the second die.

[0028] During this process, home agent nodes need to allocate data buffers to temporarily store data to be written, and going through multiple levels of home agent nodes will greatly increase the latency of completing the entire write path.

[0029] In addition, such as Figure 2 As shown, the typical path of the existing read request process includes initiator processing, directory lookup, cross-chip transfer, remote proxy processing, and serial backhaul steps.

[0030] (1) The initiating processing steps include: the computing core of the first chip initiates a read instruction, the request packet enters the on-chip network of the first chip, and is first routed to the corresponding home agent node of the first chip.

[0031] (2) The directory query steps include: the home agent node of the first crystal queries the local listening filter. If the address is found to belong to the remote second crystal, the request is redirected to the inter-crystal interface of the first crystal.

[0032] (3) The cross-chip transmission steps include: the request packet is converted by the inter-chip interface controller and transmitted to the inter-chip interface of the second chip through the micro-bump physical link.

[0033] (4) The remote proxy processing steps include: the inter-crystal interface of the second crystal sends the request to the home proxy node of the second crystal, the home proxy node of the second crystal queries the local status again, and if it determines that there is no cache hit, it sends a memory access command to the local storage controller of the second crystal.

[0034] (4) The serial backhaul steps include: after the data is read from the double data rate memory, it must pass through the storage controller of the second die, the home agent node of the second die, the inter-die interface of the second die, the inter-die interface of the first die, the home agent node of the first die, and finally reach the computing core of the first die.

[0035] In developing this application, the inventors, based on their analysis of existing cross-die memory access paths, discovered that regardless of whether the data to be accessed is data that may be shared across multiple dies, each cross-die memory access is forcibly routed through two levels of home agent nodes, and the data load and control response are coupled and follow the same serial path. The inventors further noted that in the actual operation of multi-die chips, there are numerous non-shared data access scenarios, such as program private stack space and read-only library files. This data is accessed only by the computing core of a single die and does not require a complete consistency check. However, existing technologies do not distinguish between shared and non-shared data attributes, causing non-shared data to also occupy the scarce data buffer resources of home agent nodes and generating unnecessary queuing delays during enqueueing and dequeueing.

[0036] In other words, the existing solution has the following areas for optimization: First, the funnel effect of home agent nodes: Home agent nodes not only process data but also handle complex protocol state machines. Under high load, data packets will experience queuing delays during enqueueing and dequeueing at home agent nodes. Second, path redundancy: For most non-shared data, such as the program's private stack space and read-only library files, performing consistency checks through two levels of home agent nodes is a waste of time. Third, mixed data flow and control flow: In traditional architectures, data load and state response are coupled; data must accompany state packets through all consistency nodes, increasing the physical path length of data backhaul.

[0037] Based on the above analysis, this application proposes a data processing method for multi-die chips. This method utilizes a traffic splitting approach based on shared attribute identifiers, employing methods such as splitting memory access transactions into control packets and data packets, and planning direct data paths that bypass home agent nodes based on shared attribute identifiers for non-shared data. This solves the problem in existing technologies where cross-die memory access for non-shared data is forced through two levels of home agent nodes, leading to path redundancy and excessive latency. Therefore, it can effectively reduce the serialization overhead of cross-die memory access in multi-die chips, thereby reducing the resource consumption of home agent nodes and shortening memory access latency.

[0038] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0039] Please see Figure 3 The data processing method for polycrystalline chips includes the following steps: Step S100: In response to the computing core of the first die initiating a memory access transaction to the target memory controller of the second die, the shared attribute identifier is determined.

[0040] It should be noted that when the computing core of the first die needs to access data managed by the target memory controller of the second die (i.e., the memory controller located within the second die, such as the interface connecting to Double Data Rate memory), a memory access transaction is initiated. This memory access transaction can be a read transaction (reading data from the target memory controller) or a write transaction (writing data to the target memory controller). At this time, step S100, in response to the initiation of the memory access transaction, determines a shared attribute identifier parameter that will be used later. This shared attribute identifier is a flag indicating whether the memory access data in the current memory access transaction is non-shared data. Non-shared data refers to data that, during the operation of the multi-die chip, is expected to be accessed only by the computing core of the die where the memory access transaction is currently initiated (i.e., the first die) and will not be accessed by the computing cores of other dies. Conversely, if the data may be shared by the computing cores of multiple dies, it is considered shared data.

[0041] For example, the shared attribute identifier can be generated by the home agent node of the first die according to a preset rule, and then received by the computing core for subsequent judgment. The specific value of the shared attribute identifier determines whether the subsequent process follows a split processing or a regular processing.

[0042] Please continue reading. Figure 3 Step S200: When the shared attribute identifier indicates that the memory access data in the memory access transaction is non-shared data, execute the diversion processing flow.

[0043] After determining the shared attribute identifier in step S100, step S200 will judge the shared attribute identifier. If the value of the shared attribute identifier indicates that the memory access data in the current memory access transaction is non-shared data, then the flow splitting process is triggered; otherwise (i.e., the shared attribute identifier indicates that the memory access data is data that may be shared), then the normal processing process (i.e., the data is transmitted completely through the home agent node) is executed. The flow splitting process executes different sub-processes according to the specific type of memory access transaction (write transaction or read transaction), which are defined by steps S210 and S220 respectively.

[0044] In other words, step S100 determines the shared attribute identifier at the beginning of the memory access transaction, providing a decision-making basis for distinguishing between non-shared data and shared data. Therefore, step S200 can process memory access transactions as needed, performing a traffic splitting process on memory access transactions determined to be non-shared data, while shared data still follows the regular complete consistency check path, ensuring that the correctness of cache consistency is not affected. This conditional traffic splitting mechanism guarantees correctness and, without violating the consistency protocol of multi-die chips, can reduce the serialization overhead of cross-die memory access in multi-die chips by utilizing the traffic splitting process.

[0045] Please continue reading. Figure 3 The traffic diversion process includes: Step S210: If the memory access transaction is a write transaction, the write request data of the write transaction is split into a control packet and a first data packet. The control packet is sent to the target storage controller via the home agent node. After receiving the write response returned by the target storage controller via the home agent node, the first data packet is sent to the target storage controller via a data path that bypasses the home agent node.

[0046] When step S200 determines that the current memory access transaction is a write transaction and the accessed data is non-shared data, sub-step S210 first performs a splitting operation on the write request data of the write transaction. The write request data originally contains the following information: the payload to be written (i.e., the data actually to be written to the storage controller), the address or identification information of the target storage controller, and other control information. The splitting operation separates the control flow (corresponding to the control packet) and the data flow (corresponding to the first data packet) in the write request data. Specifically, the control packet carries the control information of the write transaction (such as the identifier of the target storage controller, shared attribute identifier, etc.), but does not carry the payload of the data to be written. The control packet is small in size and is used to complete notifications and state updates related to the consistency protocol. The first data packet, on the other hand, carries the payload of the data to be written in the write transaction (i.e., the actual data content to be written), and does not carry control information or only carries a minimal routing identifier.

[0047] In step S210, after splitting the write request data into a control packet and a first data packet, the control packet is sent to the home proxy node, and then sequentially through the home proxy node of the first dies, the inter-dies interface, and the home proxy node of the second dies, finally reaching the target storage controller of the second dies. This path is a complete serial path, passing through two levels of home proxy nodes, used to maintain cache consistency.

[0048] After the computing core of the first die sends a control packet to the target storage controller of the second die, the target storage controller processes the received control packet and returns a write response along the original serial path (without bypassing the home agent node) to confirm that the control packet has been received and the corresponding consistency state update has been completed. Only after receiving this write response does the computing core of the first die send out the previously split first data packet. Unlike the control packet, the first data packet does not pass through the home agent node, but instead uses a data path that bypasses it. Specifically, the first data packet can be directly sent to the target storage controller of the second die via the inter-die interface of the first die and the inter-die interface of the second die. This path bypasses the home agent nodes of both the first and second dies, directly transmitting the data payload.

[0049] In summary, step S210 separates the control information of the write transaction from the data payload, allowing the control packet to still follow a consistent serial path to maintain protocol correctness, while the larger first data packet bypasses the home agent node and takes a direct connection path. Thus, the first data packet no longer occupies the scarce data buffer resources of the home agent node, freeing up its processing capacity. Furthermore, since the first data packet no longer experiences the enqueue and dequeue delays of the home agent node, the latency of writing data to the target storage controller is significantly reduced.

[0050] Please continue reading. Figure 3 Step S220: If the memory access transaction is a read transaction, the read request data of the read transaction is sent to the target storage controller through the home agent node, and the second data packet returned by the target storage controller based on the received read request data through the data path bypassing the home agent node, and the read response returned by the home agent node.

[0051] When step S200 determines that the current memory access transaction is a read transaction and the accessed memory data is non-shared data, sub-step S220 first sends the read request data of the read transaction along a complete serial path. This path passes through two levels of home agent nodes to complete consistency checks (confirming the location of the latest copy of the data to be read) and directory queries. The complete serial path, as described above, passes through the home agent node of the first die, the inter-die interface, the home agent node of the second die, and finally reaches the target storage controller of the second die. The read request data carries the following information: the requester identifier (i.e., the identifier of the computing core of the first die initiating the read transaction), the address information of the data to be read, and the shared attribute identifier.

[0052] Next, after receiving the read request data, the target storage controller of the second die will determine that the current read transaction is a non-shared data access based on the shared attribute identifier in the read request data, and therefore adopt a differentiated return strategy. Specifically, it will execute two independent return operations: returning the second data packet and returning the read response.

[0053] The return of the second data packet includes: the payload of the data to be read from memory by the target storage controller and packaging it into a second data packet. This second data packet bypasses the home agent node and is sent directly to the computing core of the first die via a data path that bypasses the home agent node. This path bypasses both the home agent nodes of the second die and the home agent node of the first die.

[0054] The read response includes: Simultaneously, the target storage controller returns a read response without a payload, solely to notify the home agent node that the read transaction is complete. The read response returns along the complete serial path to release tracker resources suspended by the read transaction in the home agent nodes of the first and second dies. It should be noted that these tracker resources were originally used to record the status of incomplete transactions and need to be released promptly after data is returned for use by subsequent transactions.

[0055] In summary, step S220 in a read transaction employs a separate response approach, where the data flow is transmitted directly while the control flow is transmitted serially. This design eliminates the need for data returns to travel through all consistency nodes with the state packet, thus decoupling the data flow from the control flow. Specifically, the second data packet carrying the actual data payload bypasses the two levels of home agent nodes, avoiding queuing delays during data enqueueing and dequeueing. This allows the first die's computing core to obtain the required data earlier, significantly reducing the critical path latency for read memory access. Simultaneously, the read response is still returned serially through the home agent nodes, ensuring that these nodes can promptly release suspended tracker resources and maintain the correct state machine flow of the consistency protocol. Furthermore, since the read response does not carry a payload, its processing efficiency is accelerated, preventing resource leaks or prolonged occupation that could hinder subsequent transactions and thus ensuring the stable operation of the multi-die chip system under high-concurrency memory access scenarios.

[0056] In summary, this application introduces a shared attribute identifier to distinguish whether accessed memory data is non-shared data. Based on this identifier, the data payload in write or read transactions is stripped from the serial path of the home agent node, allowing it to bypass the home agent node and be transmitted directly. Therefore, the payload of non-shared data no longer needs to pass through the home agent node at least twice and occupy its data buffer resources, as in existing technologies. This reduces queuing latency, shortens cross-die memory access latency, and frees up the processing capacity of the home agent node to serve other shared data accesses.

[0057] Based on the aforementioned scheme, in some implementations of this application, the step of determining the shared attribute identifier includes: the computing core of the first die sends the memory access request data corresponding to the memory access transaction to the home agent node of the first die, and the home agent node of the first die performs access heat analysis on the address range of the memory access request data according to the preset memory access attribute prediction mechanism to generate the shared attribute identifier.

[0058] In this implementation, the computing core of the first die first sends the memory access request data to the home proxy node of the first die. The home proxy node then performs access frequency analysis on the address range corresponding to the memory access request data. A preset memory access attribute prediction mechanism monitors the frequency and source of access to each address range, generates a shared attribute identifier based on this, and returns it to the computing core. Through this dynamic prediction based on historical access behavior, non-shared data can be accurately identified, avoiding indiscriminate routing or regular processing of all memory access transactions. This reduces the serialization overhead of cross-die memory access in multi-die chips while ensuring cache consistency, thereby reducing the resource consumption of the home proxy node and shortening the memory access latency.

[0059] For example, the preset memory access attribute prediction mechanism can be implemented using the likelyShared prediction mechanism. LikelyShared is a cache allocation hint in the ARM CHI (Coherent Hub Interface) protocol, used to indicate that the requested data "may be shared by multiple nodes" in order to optimize cache state allocation and reduce subsequent snooping overhead.

[0060] Based on the aforementioned scheme, in some implementations of this application, the step of performing access heat analysis on the address range of memory access request data to generate a shared attribute identifier includes: the home proxy node of the first die monitors the source of memory access request data for each address range. When all memory access request data received by any address range within a preset time period comes from the computing core of the same die, the shared attribute identifier for subsequent memory access request data of that address range is set to a first value indicating non-sharing; otherwise, the shared attribute identifier is set to a second value indicating possible sharing.

[0061] Understandably, this implementation provides specific rules for dynamically setting shared attribute identifiers by monitoring the source of memory access requests within an address range and combining this with a preset duration. Through this dual-judgment rule based on both time and source, this implementation can accurately distinguish between private and shared data, avoiding misclassifying frequently accessed shared data across different memory granules as non-shared data. This allows for more precise handling of memory access transactions requiring traffic splitting, while ensuring cache consistency.

[0062] Based on the aforementioned scheme, in some implementations of this application, the write request data includes payload data, a shared attribute identifier, and the node identifier of the target storage controller; the control packet carries the shared attribute identifier and the node identifier of the target storage controller, and the first data packet carries the payload data. For example... Figure 4 As shown, the steps of sending a control packet to the target storage controller via a home agent node include: the computing core of the first die sends the control packet sequentially via the home agent node of the first die, the inter-die interface, and the home agent node of the second die to the target storage controller of the second die. After receiving the write response returned by the target storage controller via the home agent node, the steps of sending the first data packet to the target storage controller via a data path bypassing the home agent node include: the computing core of the first die, in response to the received write response, sends the first data packet directly to the target storage controller via the inter-die interface, bypassing the home agent node; wherein, the write response is the information fed back by the target storage controller to the computing core of the first die in response to the received control packet, sequentially via the home agent node of the second die, the inter-die interface, and the home agent node of the first die.

[0063] Understandably, through the processing method of this implementation, the first data packet carrying the payload no longer occupies the data buffer resources of the home agent node, and also avoids the queuing delay of enqueueing and dequeueing at the home agent node, thereby reducing the cross-crystal memory access latency of write transactions, while freeing up the processing capacity of the home agent node to serve other memory access transactions that require consistency checks.

[0064] Based on the aforementioned scheme, in some implementations of this application, the second data packet carries the data requested by the read request data. For example... Figure 5 As shown, the steps for sending read request data of a read transaction to the target storage controller via the home agent node include: the first die's computing core sends the read request data sequentially through the first die's home agent node, the inter-die interface, and the second die's home agent node to the target storage controller of the second die. The steps for receiving the second data packet returned by the target storage controller based on the received read request data via a data path bypassing the home agent node, and the read response returned via the home agent node, include: the first die's computing core receives the second data packet, which is data sent directly to the first die's computing core via the inter-die interface when the target storage controller determines that the read transaction is a non-shared data access based on the received read request data; the first die's home agent receives the read response, which is information fed back to the first die's computing core by the target storage controller based on the received read request data, sequentially through the second die's home agent node, the inter-die interface, and the first die's home agent node.

[0065] In this implementation, the computing core of the first die sends the read request data sequentially through the home proxy node of the first die, the inter-die interface, and the home proxy node of the second die to the target storage controller of the second die. Then, the target storage controller, upon receiving the read request data and determining that the read transaction is a non-shared data access, performs two parallel return operations: first, it sends the second data packet directly to the computing core of the first die via the inter-die interface, bypassing the home proxy node; second, it sends the read response sequentially through the home proxy node of the second die, the inter-die interface, and the home proxy node of the first die to the computing core of the first die.

[0066] In other words, the second data packet and the read response have different return paths, which facilitates the rapid return of read data and asynchronous updates to the consistency state. Specifically, the second data packet carrying the payload no longer passes through the home agent node, avoiding queuing delays during data enqueueing and dequeueing, allowing the computing cores of the first die to obtain the required data earlier, thereby shortening the cross-die memory access latency of read transactions. At the same time, the read response is returned serially through the home agent node, ensuring the correct update of the consistency state and the timely release of tracker resources.

[0067] For example, in practical applications, the read request data initiated by the computing core of the first die can embed a return target ID (rtnTGTID). This return target ID records the physical routing address of the computing core of the first die in the on-chip network. After receiving the read request data, the target storage controller of the second die parses the return target ID from it and accordingly routes the second data packet carrying the requested data directly back to the computing core of the first die, without going through the serial path of the home agent node. In this way, the return path of the read data is further shortened, which can effectively reduce the memory access latency of read transactions.

[0068] Based on the aforementioned scheme, in some implementations of this application, the on-chip network of the multi-chip chip includes a first virtual channel disposed on the first chip and a second virtual channel disposed on the second chip. Specifically, sending the first data packet to the target storage controller via a data path bypassing the home agent node includes: sending the first data packet to the target storage controller sequentially via the first virtual channel and the second virtual channel; receiving the second data packet returned by the target storage controller via the data path bypassing the home agent node includes: receiving the second data packet returned sequentially via the second virtual channel and the first virtual channel.

[0069] Understandably, this implementation allocates dedicated virtual channels in the on-chip networks of the two dies, allocating independent transmission resources for data packets bypassing the home agent node to isolate them from consistency request traffic. Through this virtual channel isolation mechanism, this application effectively avoids interference between data packets and consistency requests on the transmission path, reduces additional queuing delays caused by channel contention, and further improves the data transmission efficiency of cross-die memory access.

[0070] Specifically, the on-chip network of the multi-chip includes a first virtual channel located on the first die and a second virtual channel located on the second die. In a write transaction, a first data packet is sent sequentially to the target storage controller via the first and second virtual channels. In a read transaction, a second data packet is received sequentially via the second and first virtual channels. In this way, data packets bypassing the home agent node no longer share the same transmission channel as consistency request traffic.

[0071] Based on the aforementioned scheme, in some implementations of this application, the dies in the multi-die chip are interconnected through an inter-die interface; the inter-die interface includes an inter-die interface controller disposed on each die and a micro-bump physical link connecting each inter-die interface controller; the data path bypassing the home agent node is a path for data transmission directly through the inter-die interface, and when the data is transmitted through the inter-die interface, after protocol conversion by the inter-die interface controller, it is transmitted across dies through the micro-bump physical link.

[0072] It is understandable that the so-called data path bypassing the home agent node refers to the path of data transmission directly through the inter-chip interface. During transmission, the data undergoes protocol conversion by the inter-chip interface controller and then completes cross-chip transmission through the micro-bump physical link. In the physical path of this implementation, the first and second data packets completely bypass the home agent nodes of the first and second chips during cross-chip transmission. This physically avoids the data packets entering the home agent nodes for protocol processing and queuing, thereby effectively reducing data transmission latency and minimizing the resource consumption of the home agent nodes.

[0073] Based on the aforementioned scheme, in some implementations of this application, the shared attribute identifier includes a first value and a second value. The first value is used to indicate that the accessed memory data is non-shared data, triggering a traffic splitting process; the second value is used to indicate that the accessed memory data is potentially shared data, triggering a regular processing process. The regular processing process includes: if the memory access transaction is a write transaction, the write request data of the write transaction is sent to the target storage controller via the home agent node; and after receiving the write response returned by the target storage controller via the home agent node, the data requested to be written in the write request data is sent to the target storage controller via the home agent node; if the memory access transaction is a read transaction, the read request data of the read transaction is sent to the target storage controller via the home agent node, and the target storage controller, based on the received read request data, returns data requested to be read and the corresponding read response via the home agent node.

[0074] In this implementation, two different processing flows are distinguished by the first and second values ​​of the shared attribute identifier, allowing the multi-die chip to select the appropriate processing flow based on the memory access data. The first value indicates that the memory access data is non-shared data, triggering a split processing flow: the first data packet of a write transaction bypasses the home agent node and is transmitted directly; the second data packet of a read transaction also bypasses the home agent node and is transmitted directly. The second value indicates that the memory access data is potentially shared data, triggering a regular processing flow. In the regular processing flow, if it is a write transaction, the write request data is sent to the target storage controller via the home agent node, and after receiving the write response, the requested write data is also sent to the target storage controller via the home agent node. If it is a read transaction, the read request data is sent to the target storage controller via the home agent node, and the target storage controller returns the requested read data and the corresponding read response via the home agent node.

[0075] In other words, this implementation uses a switching mechanism between the split processing flow and the regular processing flow to enable fast access to non-shared data with low latency and low resource consumption, while maintaining a complete consistency check path for potentially shared data, thus achieving a balance between performance optimization and consistency guarantee.

[0076] Based on the aforementioned scheme, in some implementations of this application, the target storage controller includes a data buffer; when the memory access transaction is a write transaction and the shared attribute identifier indicates non-shared data, after receiving the first data packet, the target storage controller directly writes the payload data carried by the first data packet into the data buffer without going through a consistency status query.

[0077] This implementation simplifies the handling of write transactions for non-shared data on the target storage controller side, omitting the consistency query step. This allows write transactions to bypass consistency-related processing logic on the receiving end, further shortening the data write path. It's important to note that since non-shared data is not accessed by the computing cores of other dies, omitting the consistency state query is safe, while simultaneously reducing the processing overhead of the target storage controller and lowering the overall completion latency of write transactions.

[0078] To enable those skilled in the art to more intuitively understand this application, a specific example will be provided below. This example is an exemplary demonstration combining the overall technical paradigm of this application with some optional implementation details. It should be noted that the following demonstration is intended to aid understanding and does not constitute an exhaustive list of all embodiments of this application, nor does it imply that this application must include all the details described below in its specific implementation.

[0079] In this example, a memory access attribute prediction mechanism (likelyShared flag) is added to the compute core side, which allows memory access transactions to be split into a data stream and a control stream based on the shared attribute identifier. The data stream uses point-to-point shortest path routing, while the control stream is responsible for maintaining the consistency logic of the home agent node, thereby enabling data bypassing at the home agent node.

[0080] like Figure 4 As shown, the write request path in this example is as follows: When the compute core initiates a Direct Write Transfer (DWT) request and determines that the data is non-shared (likelyShared=0) based on the shared attribute identifier, it performs transaction splitting: the compute core splits the write transaction into a Bypass Data packet carrying a payload and a Control Write packet without a payload.

[0081] Regarding the direct data path, the target ID (the ID information of the target node, which the router can use to determine how requests, data, or responses should be routed on the NOC network) of the remote storage controller obtained through the write response is used to bypass the data packets directly into the Network on Chip (NOC). The packets then pass through the inter-chip interface of the first chip and the inter-chip interface of the second chip, bypassing the home agent node of the second chip, and are directly delivered to the storage controller of the second chip.

[0082] In this way, writing data no longer consumes the tracker resources and data buffer of the home agent node, reducing the residence time of data between multi-level cache nodes. Regarding consistent asynchronous updates, the write control packet is sent to the corresponding home agent node, which only updates the consistency status bits based on the packet, such as marking the address as invalid or updating the directory, without actually touching large data blocks.

[0083] like Figure 5 As shown, the read request path in this example is as follows: Once data is read from remote Double Data Rate (DDR) memory, a bidirectional transmission is performed: the storage controller routes the data packet directly back to the compute core of the first die based on the return target identifier (rtnTGTID, the ID of the initiating core) and bypass flag (Bypass_Flag) in the request header. Simultaneously, asynchronous notification is executed: the storage controller synchronously sends a response signal to the home agent node, informing it that the transaction is complete and releasing any pending tracker resources in the home agent node. This allows the compute core to obtain data earlier than the home agent node's protocol processing time, significantly reducing critical path latency.

[0084] In other words, the key implementation details in the write and read request paths in this example lie in the identifier mapping and routing logic. Specifically, to implement the bypass processing logic in this example, the hardware needs to support the following logic: Return Target ID (rtnTGTID): This field is added to the read request header to record the physical routing address of the initiating compute core. The storage controller uses this identifier to achieve radial direct data return.

[0085] The shared attribute identifier prediction mechanism (likelyShared prediction mechanism) works as follows: The home agent node dynamically monitors the access frequency of each address segment. If an address segment is accessed by only a single compute core on a single die for an extended period, the home agent node sets the shared attribute identifier field (likelyShared field) of read requests for that address segment downstream to zero. Requests for that address segment will then be bypassed. For write requests, the home agent node of the first die sets the shared attribute identifier field when sending a write response upstream, and simultaneously sets the return target identifier to the identifier of the storage controller of the second die. This allows the compute core to directly send data downstream based on the return target identifier (rtnTGTID) and the shared attribute identifier field (likelyShared field) in the write response.

[0086] As illustrated by this example, in terms of write performance, direct write transmission of data directly into memory avoids queuing at home agent nodes during the consistency window. Bypassed data no longer occupies the valuable data buffer of the home agent node, allowing it to handle more concurrent control requests and improving the overall throughput of the multi-chip system. Regarding read performance, in dual-chip or multi-chip systems, the round-trip path for reading data across chips is greatly simplified. Experiments predict that average memory access latency can be reduced by 20%-35% under typical server workloads. In terms of power consumption and bandwidth efficiency, unnecessary forwarding layers for large data packets in the on-chip network are reduced. Since data packets no longer enter the home agent node for parsing and repackaging, dynamic switching power consumption is reduced, and network bandwidth around the home agent node is freed up. Regarding addressing the multi-chip scalability bottleneck, as the number of chips increases (e.g., in an 8-chip architecture), the latency of traditional serial paths increases exponentially. The point-to-point backhaul mechanism in this application limits memory access latency only to the number of physical link hops, providing excellent scalability.

[0087] like Figure 6 As shown in the embodiments of this application, a multi-chip is also provided, which includes multiple chips. Each chip includes at least one computing core, at least one home agent node, an on-chip network, at least one memory controller, and an inter-chip interface for connecting with other chips. The computing core is used to implement any of the data processing methods for multi-chip provided by the above-described implementations.

[0088] It is understood that this application embeds any of the data processing methods for multi-die chips provided by the various implementation methods described above into the computing core of the multi-die chip, enabling the multi-die chip to execute the split processing flow itself. By integrating this method into the chip hardware, the multi-die chip can autonomously reduce the serialization processing overhead of cross-die memory access in the multi-die chip without relying on external control, thereby reducing cross-die memory access latency and releasing home agent node resources.

[0089] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A data processing method for polycrystalline chips, characterized in that, include: In response to the computing core of the first die initiating a memory access transaction to the target memory controller of the second die, the shared attribute identifier is determined; When the shared attribute identifier indicates that the memory access data in the memory access transaction is non-shared data, a traffic splitting process is executed. The traffic splitting process includes: If the memory access transaction is a write transaction, the write request data of the write transaction is split into a control packet and a first data packet, and the control packet is sent to the target storage controller via the home agent node. After receiving the write response returned by the target storage controller via the home agent node, the first data packet is sent to the target storage controller via a data path that bypasses the home agent node. If the memory access transaction is a read transaction, the read request data of the read transaction is sent to the target storage controller via the home proxy node, and the target storage controller receives the second data packet returned by the target storage controller based on the received read request data via a data path bypassing the home proxy node, and the read response returned by the home proxy node.

2. The data processing method according to claim 1, characterized in that, The step of determining the shared attribute identifier includes: the computing core of the first die sends the memory access request data corresponding to the memory access transaction to the home proxy node of the first die, and the home proxy node of the first die performs access popularity analysis on the address range of the memory access request data according to a preset memory access attribute prediction mechanism to generate the shared attribute identifier.

3. The data processing method according to claim 2, characterized in that, The step of performing access popularity analysis on the address range of the memory access request data to generate the shared attribute identifier includes: The home proxy node of the first die monitors the source of memory access request data for each address segment; When all memory access request data received by any address segment within a preset time period comes from the computing core of the same die, the shared attribute identifier for subsequent memory access request data of that address segment is set to a first value that indicates non-sharing; otherwise, the shared attribute identifier is set to a second value that indicates possible sharing.

4. The data processing method according to claim 1, characterized in that, The write request data includes payload data, a shared attribute identifier, and a node identifier of the target storage controller; the control packet carries the shared attribute identifier and the node identifier of the target storage controller, and the first data packet carries the payload data; The step of sending the control packet to the target storage controller via the home agent node includes: the computing core of the first die sending the control packet sequentially via the home agent node of the first die, the inter-die interface and the home agent node of the second die to the target storage controller of the second die. The step of sending the first data packet to the target storage controller via a data path bypassing the home agent node after receiving the write response returned by the target storage controller through the home agent node includes: the computing core of the first die responding to the received write response by sending the first data packet directly to the target storage controller via the inter-die interface; wherein, the write response is information fed back by the target storage controller to the computing core of the first die in response to the received control packet, sequentially via the home agent node of the second die, the inter-die interface, and the home agent node of the first die.

5. The data processing method according to claim 1, characterized in that, The second data packet carries the data requested by the read request data; The step of sending the read request data of the read transaction to the target storage controller via the home agent node includes: the computing core of the first die sends the read request data sequentially via the home agent node of the first die, the inter-die interface and the home agent node of the second die to the target storage controller of the second die. The step of receiving the second data packet returned by the target storage controller based on the received read request data, bypassing the data path of the home proxy node, and the read response returned by the home proxy node, includes: The computing core of the first die receives the second data packet. The second data packet is data that the target storage controller sends directly to the computing core of the first die through the inter-die interface when it learns that the read transaction is a non-shared data access based on the received read request data. The home agent of the first die receives the read response, which is the information fed back by the target storage controller to the computing core of the first die in sequence through the home agent node of the second die, the inter-die interface, and the home agent node of the first die, based on the received read request data.

6. The data processing method according to claim 1, characterized in that, The on-chip network of the multi-chip chip includes a first virtual channel disposed on the first chip and a second virtual channel disposed on the second chip; The step of sending the first data packet to the target storage controller via a data path that bypasses the home agent node includes: sending the first data packet to the target storage controller sequentially via the first virtual channel and the second virtual channel; Receiving the second data packet returned by the target storage controller via a data path bypassing the home agent node includes: receiving the second data packet returned sequentially via the second virtual channel and the first virtual channel.

7. The data processing method according to claim 1, characterized in that, The dies in the multi-die chip are interconnected via inter-die interfaces. The inter-die interface includes an inter-die interface controller disposed on each die and a micro-bump physical link connecting each inter-die interface controller. The data path that bypasses the home agent node is the path for data transmission directly through the inter-die interface. When the data is transmitted through the inter-die interface, it is transmitted across dies after protocol conversion by the inter-die interface controller through the micro-bump physical link.

8. The data processing method according to claim 1, characterized in that, The shared attribute identifier includes a first value and a second value; the first value is used to characterize that the accessed memory data is non-shared data, triggering the traffic splitting process. The second value is used to characterize the memory access data as potentially shared data, triggering a regular processing flow; The conventional processing flow includes: If the memory access transaction is a write transaction, the write request data of the write transaction is sent to the target storage controller via the home agent node, and after receiving the write response returned by the target storage controller via the home agent node, the data requested to be written in the write request data is sent to the target storage controller via the home agent node. If the memory access transaction is a read transaction, the read request data of the read transaction is sent to the target storage controller through the home agent node, and the target storage controller receives the data requested to be read and the corresponding read response from the home agent node based on the received read request data.

9. The data processing method according to claim 1, characterized in that, The target storage controller includes a data buffer; when the memory access transaction is a write transaction and the shared attribute identifier indicates non-shared data, after receiving the first data packet, the target storage controller directly writes the payload data carried by the first data packet into the data buffer without going through a consistency status query.

10. A polycrystalline chip, characterized in that, It includes multiple chips, each chip including at least one computing core, at least one home agent node, on-chip network, at least one storage controller, and inter-chip interface for connecting with other chips; wherein the computing core is used to implement the data processing method as described in any one of claims 1-9.

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