Voltage controlled delay cell circuit and delay-locked loop
Patent Information
- Application Number
- CN202610721745.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-25
- Publication Date
- 2026-09-01
AI Technical Summary
[0009]本发明要解决的技术问题是现有传统电流饥饿型压控延迟单元电平反转耗时久、噪声大，进而导致延迟锁相环时钟抖动严重、精度低的技术问题
本发明针对传统电流饥饿型压控延迟单元的固有缺陷，在其核心反相器电路基础上，创新性地增设了由PM0S5、PM0S6、NM0S5、NM0S6构成的电流调控模块。该模块的核心作用在于为反相器的充放电通路提供一条持续导通的、恒定的小电流I1支路，使电路在静态和动态工作过程中始终脱离MOS管的截止区，维持在亚阈值区或线性区边缘。当输入信号IN发生电平翻转时，反相器主通路的NMOS/PMOS管开始导通，而电流调控模块中的NM0S5、NM0S6/PM0S5、PM0S6管由于预偏置状态，能够快速从线性区转入饱和区，形成叠加的充放电电流，从而显著加快电路的电流响应速度，缩短输出节点电平的上升/下降时间。通过这种方式，电路避免了传统结构中因MOS管从截止区缓慢开启而导致的电平反转拖尾效应，大幅提升了信号边沿的陡峭程度。
Smart Images
Figure CN122678699A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-noise voltage-controlled delay unit circuit and a delay phase-locked loop (DLL) for use in a delay phase-locked loop (DLL). Background Technology
[0002] Delay-Locked Loops (DLLs), as the core circuit for achieving precise clock synthesis and synchronization in integrated circuit systems, are widely used in various high-performance integrated circuits such as microprocessors, memory, and communication chips. Their performance directly determines the operational stability and data transmission reliability of the entire electronic system. The clock signal, as the "pulse" of an integrated circuit, directly affects the chip's processing speed, power consumption control, and signal integrity through its accuracy and jitter. DLLs, by adjusting the delay and phase locking of the input clock signal, can achieve precise clock signal synchronization, phase calibration, and frequency synthesis, providing a highly stable and accurate clock reference for the entire system. They are an indispensable core module of modern Very Large Scale Integration (VLSI) circuits.
[0003] In the overall architecture of a DLL, the Voltage-Controlled Delay Line (VCDL) is the key core module for achieving delay adjustment and phase locking. Its main function is to dynamically adjust its own delay based on the externally input control voltage signal, thereby calibrating the phase offset of the input clock signal and ultimately synchronizing the DLL's output clock with the input clock. Structurally, a VCDL is typically composed of multiple identical and consistent Voltage-Controlled Delay Cells connected in series. The total delay of the entire VCDL is equal to the product of the delay of a single VCDL cell and the number of cells. Therefore, the performance parameters of a single VCDL cell (such as delay stability, noise level, and response speed) directly determine the overall performance of the VCDL, thus affecting the overall clock quality of the DLL.
[0004] Because voltage-controlled delay units (VCDLs) are subject to various interferences during operation, including device noise, power supply noise, and environmental noise, these noises directly contribute to the delay adjustment process, causing random fluctuations in the VCDL output delay. This leads to clock jitter in the DLL output clock signal. Clock jitter causes unpredictable offsets in the rising and falling edges of the clock signal, disrupting clock synchronization. When the jitter exceeds the system's allowable range, it can result in data sampling errors, increased signal transmission bit error rate, severely degrading the performance of the entire integrated circuit system, and even causing the system to malfunction. Therefore, developing low-noise, high-stability VCDLs is a key breakthrough for improving DLL clock accuracy, reducing clock jitter, and optimizing the overall performance of the integrated circuit system.
[0005] Currently, most existing delay phase-locked loops (VCDLs) use traditional current-starved voltage-controlled delay units (VCDs) as their core components. The working principle of this type of VCD is relatively simple. Its core design idea is to convert the externally input control voltage Vctrl into a corresponding control current I0 through a current conversion circuit. This control current I0 is then applied to the inverter module. By adjusting the magnitude of the control voltage Vctrl, the amplitude of the control current I0 is changed, thereby adjusting the operating current intensity of the inverter and ultimately achieving precise control of the inverter's delay time, thus realizing the core function of voltage-controlled delay. This type of VCD was widely used in early integrated circuit design due to its simple structure, low design cost, and ease of integration.
[0006] However, as integrated circuits rapidly develop towards higher frequencies, higher integration, and lower power consumption, the inherent structural defects of traditional current-starved voltage-controlled delay units (VCDs) have become increasingly apparent, making it difficult to meet the application requirements of high-performance DLLs. The most prominent problems are high noise and severe clock jitter, leading to insufficient clock accuracy in the DLL. Specifically, in the process of level inversion (i.e., from high to low or from low to high), the inverter in a traditional VCD requires a relatively long time to invert the level due to limitations in its circuit structure. According to inverter noise theory and actual test data, the level inversion time of the inverter is positively correlated with the introduced noise intensity. That is, the longer the inversion time, the longer the inverter is subjected to interference from device thermal noise, power supply fluctuation noise, etc., during the inversion process, and the greater the introduced noise.
[0007] These introduced noises directly cause random fluctuations in the delay of the voltage-controlled delay unit (VCDL). The delay fluctuation of a single VCDL is amplified stage by stage after multiple units are connected in series, eventually propagating to the entire VCDL and causing severe phase jitter in the DLL output clock, resulting in a significant decrease in clock accuracy. Furthermore, traditional current-starved VCDLs suffer from limited delay adjustment range and poor temperature stability, further restricting the application of DLLs in high-performance integrated circuits. Therefore, a novel low-noise VCDL design is urgently needed to address the shortcomings of existing technologies. Summary of the Invention
[0008] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0009] The technical problem to be solved by this invention is that the existing traditional current-starved voltage-controlled delay unit has a long time to reverse the level and high noise, which leads to serious clock jitter and low accuracy of the delay phase-locked loop.
[0010] To solve the above technical problems, the present invention provides a voltage-controlled delay unit circuit, comprising: The first terminal of the first type MOS1 and the third type MOS3 are connected to the power supply, and the third terminal is connected to the control voltage. The second terminal of the first type MOS1 is connected to the first terminal of the first type MOS2, and the second terminal of the first type MOS3 is connected to the first terminal of the first type MOS4. The second terminal of the first type MOS2 is connected to the second terminal of the second type MOS1, the third terminal of the first type MOS4, and the third terminal of the second type MOS3; The third terminal of the first-type MOS2 and the second-type MOS1 is connected to the input terminal IN; the second terminal of the first-type MOS4 and the second terminal of the second-type MOS3 are connected to the output terminal OUT. The first terminal of the second type MOS1 is connected to the second terminal of the second type MOS2, the third terminal of the second type MOS2 is connected to the bias voltage, and the first terminal of the second type MOS2 is grounded. The first terminal of the second type MOS3 is connected to the second terminal of the second type MOS4, the third terminal of the second type MOS4 is connected to the bias voltage, and the first terminal of the second type MOS4 is grounded. Its characteristic is that it further includes: The first terminal of the first type MOS5 is connected to the power supply, the third terminal is connected to the control voltage, and the second terminal is connected to the second terminal of the second type MOS1. The first terminal of the first type MOS6 is connected to the power supply, the third terminal is connected to the control voltage, and the second terminal is connected to the second terminal of the second type MOS3. The first terminal of the second type MOS5 is connected to the second terminal of the first type MOS1, the third terminal is connected to the bias voltage, and the first terminal is grounded. The first terminal of the second type MOS6 is connected to the second terminal of the first type MOS3, the third terminal is connected to the bias voltage, and the first terminal is grounded.
[0011] Preferably, the first type of MOS in the voltage-controlled delay unit circuit is PMOS, and the second type of MOS is NMOS.
[0012] Preferably, in the voltage-controlled delay unit circuit, the first terminal is the source, the second terminal is the drain, and the third terminal is the gate.
[0013] This invention provides a delay phase-locked loop (PLL), comprising a phase detector, a charge pump, a loop filter, and at least one voltage-controlled delay unit (VCD) circuit. The phase detector receives a reference clock ref_clk and outputs a phase difference signal to the charge pump. The charge pump generates a control voltage Vctrl, which is filtered by the loop filter and then input to the VCD circuit. The VCD circuit outputs a delayed clock vcdl_clk and feeds it back to the phase detector. The VCD circuit is the VCD circuit described in any one of claims 1-3.
[0014] Based on the above technical solution, the working principle of the present invention is explained as follows; This invention addresses the inherent shortcomings of traditional current-starved voltage-controlled delay units by innovatively adding a current regulation module composed of PMOS5, PMOS6, NMOS5, and NMOS6 to the core inverter circuit. The core function of this module is to provide a continuously conducting, constant small current I1 branch for the inverter's charging and discharging path, ensuring the circuit remains outside the cutoff region of the MOSFETs during both static and dynamic operation, maintaining it at the edge of the subthreshold or linear region. When the input signal IN undergoes a level flip, the NMOS / PMOS transistors in the inverter's main path begin to conduct. Meanwhile, the NMOS5, NMOS6 / PM0S5, and PMOS6 transistors in the current regulation module, due to their pre-biased state, can quickly transition from the linear region to the saturation region, forming a superimposed charging and discharging current. This significantly accelerates the circuit's current response speed and shortens the rise / fall time of the output node level. In this way, the circuit avoids the level inversion tailing effect caused by the slow turn-on of the MOSFETs from the cutoff region in traditional structures, greatly improving the steepness of the signal edges.
[0015] This invention achieves fundamental optimization of the noise performance of voltage-controlled delay units (VCDs) through the aforementioned working principle. By significantly shortening the inverter's level inversion time, the circuit's sensitivity to power supply noise, substrate noise, and thermal noise is greatly reduced, thereby directly reducing the phase noise and clock jitter of the delay phase-locked loop (DLL) output clock. Under typical process conditions, simulation tests were conducted with a 1.5V power supply voltage and a 100MHz clock frequency. The clock jitter performance of this invention applied to the DLL achieved: peak-to-peak jitter of 11.118ps, period jitter (RMS) of 2.037ps, and period jitter (RMS) of 1.854ps. In contrast, existing traditional VCDs lack a constant low-current sustaining mechanism, causing the MOSFET to easily enter a deep cutoff region before signal inversion, resulting in a slow turn-on process. This significantly increases the level inversion time, lengthens the noise coupling path, and ultimately causes severe clock jitter and insufficient output accuracy in the DLL, failing to meet the performance requirements of high-speed, low-jitter clock systems. Attached Figure Description
[0016] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0017] Figure 1 This is a schematic diagram of the existing technology structure.
[0018] Figure 2 This is a schematic diagram of the structure of the present invention.
[0019] Explanation of reference numerals in the attached figures PMOS1~PMOS6 represent different PMOS transistors; NMOS1 to NMOS6 represent different NMOS transistors. Detailed Implementation
[0020] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.
[0021] First embodiment; refer to Figure 2 As shown, the present invention provides a voltage-controlled delay unit circuit, comprising: The sources of PMOS1 and PMOS3 are connected to the power supply, and the gates are connected to the control voltage. The drain of PMOS1 is connected to the source of PMOS2, and the drain of PMOS3 is connected to the source of PMOS4; The drain of PMOS2 is connected to the drain of NMOS1, the gate of PMOS4, and the gate of NMOS3; The gates of PMOS2 and NMOS1 are connected to the input terminal IN, and the drains of PMOS4 and NMOS3 are connected to the output terminal OUT. The source of NMOS1 is connected to the drain of NMOS2, the gate of NMOS2 is connected to the bias voltage, and the source of NMOS2 is grounded. The source of NMOS3 is connected to the drain of NMOS4, the gate of NMOS4 is connected to the bias voltage, and the source of NMOS4 is grounded. PMOS5 has its source connected to the power supply, its gate connected to the control voltage, and its drain connected to the drain of NMOS1. The source of PMOS6 is connected to the power supply, the gate is connected to the control voltage, and the drain is connected to the drain of NMOS3. The source of NMOS5 is connected to the drain of PMOS1, the gate is connected to the bias voltage, and the source is grounded. The source of NMOS6 is connected to the drain of PMOS3, the gate is connected to the bias voltage, and the source is grounded.
[0022] Second embodiment; This invention provides a delay phase-locked loop, including a phase detector, a charge pump, a loop filter, and at least one voltage-controlled delay unit circuit. The phase detector receives a reference clock ref_clk and outputs a phase difference signal to the charge pump. The charge pump generates a control voltage Vctrl, which is filtered by the loop filter and then input to the voltage-controlled delay unit circuit. The voltage-controlled delay unit circuit outputs a delayed clock vcdl_clk and feeds it back to the phase detector. The voltage-controlled delay unit circuit is the voltage-controlled delay unit circuit described in the first embodiment.
[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.
[0024] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A voltage-controlled delay unit circuit, characterized in that, include: The first terminal of the first type MOS1 and the third type MOS3 are connected to the power supply, and the third terminal is connected to the control voltage. The second terminal of the first type MOS1 is connected to the first terminal of the first type MOS2, and the second terminal of the first type MOS3 is connected to the first terminal of the first type MOS4. The second terminal of the first type MOS2 is connected to the second terminal of the second type MOS1, the third terminal of the first type MOS4, and the third terminal of the second type MOS3; The third terminal of the first-type MOS2 and the second-type MOS1 is connected to the input terminal IN; the second terminal of the first-type MOS4 and the second terminal of the second-type MOS3 are connected to the output terminal OUT. The first terminal of the second type MOS1 is connected to the second terminal of the second type MOS2, the third terminal of the second type MOS2 is connected to the bias voltage, and the first terminal of the second type MOS2 is grounded. The first terminal of the second type MOS3 is connected to the second terminal of the second type MOS4, the third terminal of the second type MOS4 is connected to the bias voltage, and the first terminal of the second type MOS4 is grounded. Its characteristic is that it further includes: The first terminal of the first type MOS5 is connected to the power supply, the third terminal is connected to the control voltage, and the second terminal is connected to the second terminal of the second type MOS1. The first terminal of the first type MOS6 is connected to the power supply, the third terminal is connected to the control voltage, and the second terminal is connected to the second terminal of the second type MOS3. The first terminal of the second type MOS5 is connected to the second terminal of the first type MOS1, the third terminal is connected to the bias voltage, and the first terminal is grounded. The first terminal of the second type MOS6 is connected to the second terminal of the first type MOS3, the third terminal is connected to the bias voltage, and the first terminal is grounded.
2. The voltage-controlled delay unit circuit as described in claim 1, characterized in that: The first type of MOS is PMOS, and the second type of MOS is NMOS.
3. The voltage-controlled delay unit circuit as described in claim 2, characterized in that: The first terminal is the source, the second terminal is the drain, and the third terminal is the gate.
4. A delay phase-locked loop, comprising a phase detector, a charge pump, a loop filter, and at least one voltage-controlled delay unit circuit, wherein the phase detector receives a reference clock ref_clk and outputs a phase difference signal to the charge pump, the charge pump generates a control voltage Vctrl which is filtered by the loop filter and then input to the voltage-controlled delay unit circuit, and the voltage-controlled delay unit circuit outputs a delayed clock vcdl_clk which is fed back to the phase detector, characterized in that: The voltage-controlled delay unit circuit is the voltage-controlled delay unit circuit according to any one of claims 1-3.