Signal processing and de-processing method, communication device and storage medium

Abstract

The application provides a signal processing and deprocessing method, a communication device and a storage medium. The signal processing method comprises the following steps: adding a CRC bit sequence to a transport block to obtain an added transport block; sequentially performing code block segmentation and CRC bit sequence addition on the added transport block to obtain a code block bit sequence; performing LDPC encoding on each code block bit sequence to obtain a mother code codeword; performing bit selection on each mother code codeword to obtain a bit selection sequence; and performing code block interleaving on each bit selection sequence to obtain a code block interleaving sequence; wherein whether the code block interleaving supports sub-block interleaving is determined according to predefined condition information.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a signal processing and deprocessing method, communication equipment, and storage medium. Background Technology

[0002] The sixth-generation mobile communication system, or 6G, is the next generation of mobile communication systems. Its standards will be developed by the renowned 3GPP international standards organization, and large-scale commercial use of 6G is expected worldwide around 2030. The 6G international standard and mobile communication system can promote the rapid development and maturity of the industrial internet, the Internet of Things, artificial intelligence, virtual reality, autonomous driving, robotics, and the metaverse. In 2023, the International Telecommunication Union (ITU) Radio Sector released a recommendation for the 6G framework and overall objectives, outlining design requirements for 6G technology research and development. The spectral efficiency of 6G needs to be 1.5 times and 3 times that of 5G, thus necessitating further improvements in the performance gain of 6G channel coding.

[0003] Problem: In existing 5G New Radio Access (NR) communication systems, the coding and modulation modules are relatively independent. While each module maintains a near-optimal design, the overall design is not optimal. Therefore, there is a lack of comprehensive consideration for coding and modulation optimization while maintaining compatibility with existing channel coding designs. Thus, it is necessary to consider introducing a new interleaver to optimize the link performance of LDPC codes. Summary of the Invention

[0004] In view of this, embodiments of this application provide a signal processing and deprocessing method, a communication device, and a storage medium, which optimize the link performance of LDPC codes.

[0005] This application provides a signal processing method, the method comprising:

[0006] Add a CRC bit sequence to the transport block to obtain the transport block with the added bits.

[0007] The added transmission block is sequentially segmented into code blocks and CRC bit sequences are added to obtain the code block bit sequence;

[0008] Each bit sequence of the code block is LDPC encoded to obtain the mother codeword;

[0009] Perform bit selection on each of the mother codewords to obtain a bit selection sequence;

[0010] Each bit selection sequence is interleaved with code blocks to obtain a code block interleaved sequence;

[0011] Specifically, it is determined whether the code block interleaving supports sub-block interleaving based on predefined condition information.

[0012] This application provides a signal processing method, the method comprising:

[0013] Add a CRC bit sequence to the transport block to obtain the transport block with the added bits.

[0014] The added transmission block is sequentially segmented into code blocks and CRC bit sequences are added to obtain the code block bit sequence;

[0015] Each bit sequence of the code block is LDPC encoded to obtain the mother codeword;

[0016] Perform bit selection on each of the mother codewords to obtain a bit selection sequence;

[0017] Each bit selection sequence is interleaved with code blocks to obtain a code block interleaved sequence;

[0018] Specifically, the bit selection is determined based on predefined condition information to determine whether sub-block interleaving is supported.

[0019] This application provides a signal deprocessing method, the method comprising:

[0020] The soft bit sequence of the code block is interleaved with the decoder block to obtain the deinterleaved soft codeword sequence;

[0021] The deinterleaved soft codeword sequence is subjected to debit selection to obtain the mother codeword;

[0022] The mother codeword is subjected to LDPC decoding to obtain the decoded code block;

[0023] The decoded code block is segmented and verified to obtain the added transmission block;

[0024] The added transport block is de-verified to obtain the transport block;

[0025] Specifically, it is determined whether the decoding block interleaving supports sub-block deinterleaving based on predefined condition information.

[0026] This application provides a signal deprocessing method, the method comprising:

[0027] The soft bit sequence of the code block is interleaved with the decoder block to obtain the deinterleaved soft codeword sequence;

[0028] The deinterleaved soft codeword sequence is subjected to debit selection to obtain the mother codeword;

[0029] The mother codeword is subjected to LDPC decoding to obtain the decoded code block;

[0030] The decoded code block is segmented and verified to obtain the added transmission block;

[0031] The added transport block is de-verified to obtain the transport block;

[0032] Specifically, the determination of whether the deinterleaving bit selection supports sub-block deinterleaving is based on predefined condition information.

[0033] This application provides a communication device, including: one or more processors;

[0034] The one or more processors implement the method described in any of the above embodiments.

[0035] This application provides a storage medium storing a computer program, which, when executed by a processor, implements the methods described in any of the above embodiments. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a resource grid implementation provided by existing technology;

[0037] Figure 2 A schematic diagram of the architecture of a communication system provided in this application embodiment;

[0038] Figure 3 This is a flowchart of a signal processing method provided in an embodiment of this application;

[0039] Figure 4 This is a flowchart of another signal processing method provided in an embodiment of this application;

[0040] Figure 5 This is a flowchart of yet another signal processing method provided in the embodiments of this application;

[0041] Figure 6 This is a comparative diagram of performance gain under the same code rate and different modulation orders provided in an embodiment of this application;

[0042] Figure 7 This is a flowchart of a signal deprocessing method provided in an embodiment of this application;

[0043] Figure 8 This is a flowchart of another signal deprocessing method provided in the embodiments of this application;

[0044] Figure 9 This is a schematic diagram of another signal deprocessing method provided in the embodiments of this application;

[0045] Figure 10 This is a schematic diagram of the structure of a signal processing device provided in an embodiment of this application;

[0046] Figure 11 This is a schematic diagram of the structure of a signal deprocessing device provided in an embodiment of this application;

[0047] Figure 12 This is a schematic diagram of the structure of a wireless communication transmitting device provided in an embodiment of this application;

[0048] Figure 13 This is a schematic diagram of the structure of a wireless communication receiving device provided in an embodiment of this application. Detailed Implementation

[0049] The embodiments of this application will be described below with reference to the accompanying drawings. The examples given are for illustrative purposes only and are not intended to limit the scope of this application.

[0050] Wireless communication systems are widely deployed to provide a variety of telecommunications services, such as telephone, video, data, messaging, and broadcasting. Typical wireless communication systems may employ multiple access technologies that enable communication with multiple users by sharing available system resources. Examples of such multiple access technologies include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal Frequency Division Multiple Access (OFDMA) systems, Single Carrier Frequency Division Multiple Access (SC-FDMA) systems, and Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) systems. These multiple access technologies have been adopted by various telecommunications standards to provide a common protocol enabling different wireless devices to communicate at the city, national, regional, and even global levels.

[0051] The cellular concept enabled the rapid development of mobile communications, which can be roughly divided into the following stages:

[0052] The first generation of mobile communication systems used frequency division multiple access (FDMA) analog modulation.

[0053] The second-generation cellular system adopted time division multiple access (TDMA) and code division multiple access (CDMA) digital modulation methods, which improved system capacity and adopted independent channel signaling transmission, greatly improving system performance.

[0054] Third-generation mobile communication systems can provide greater system capacity to meet the requirements of multimedia communication.

[0055] Fourth-generation mobile communication systems primarily employ OFDM and MIMO technologies, providing truly high-speed broadband access. The first version of LTE was Release 8 (Rel-8), completed in September 2007. Due to widespread interest from operators, Long-Term Evolution (LTE) gradually became the world's mainstream 4G mobile communication standard. Later, LTE-Advanced was standardized. As a significant technological advancement, the LTE-Advanced standard was released as Release 10, with performance indicators fully meeting the requirements of IMT-Advanced (Rel-10 LTE achieves a peak rate of 375 Mbit / s with a single antenna and a bandwidth of 5 0MHz). LTE / LTE-Advanced largely retains the Turbo codes used in 3G for forward error correction in the data channel. LTE has made some optimizations to the Turbo code structure, reducing decoding complexity and improving performance to some extent. The control channel uses tail-biting convolutional codes, which slightly improve performance compared to classic zero-tail bit convolutional codes because they do not require additional tail bits.

[0056] Fifth-generation (5G) mobile communication systems are a new generation of broadband mobile communication technology characterized by high speed, low latency, and massive connectivity. 5G communication infrastructure serves as the network infrastructure for realizing the interconnection of humans, machines, and things. The three main application scenarios of 5G include: Enhanced Mobile Broadband (eMBB), Ultra-Reliable Low-Latency Communications (uRLLC), and Massive Machine-Type Communications (mMTC). To support high-speed transmission and better coverage, key 5G technologies employ LDPC, the Polar channel coding scheme, and high-performance massive MIMO technology. To support low latency and high reliability, 5G utilizes technologies such as short frames, fast feedback, and multi-layer / multi-site data retransmission.

[0057] 6G, or the sixth-generation mobile communication standard, also known as sixth-generation mobile communication technology, can promote the rapid development and maturity of the industrial internet, the Internet of Things, artificial intelligence, virtual reality, autonomous driving, robotics, and the metaverse. The goal of 6G technology is to achieve higher data transmission speeds, lower latency, higher reliability, wider network connectivity, and better security in the future.

[0058] The wireless interface is often the decisive factor in a mobile communication system; in other words, the evolution of wireless interface technology directly determines the transformation of mobile communication systems. A wireless interface typically includes transceivers (base stations and terminals) and an air channel. The transceiver itself consists of three parts: baseband, intermediate frequency (IF), and radio frequency (RF). In wireless interface technology, baseband processing is often the most crucial; therefore, this discussion will focus on the baseband processing flow.

[0059] Based on the encoding method used by the transmitting end to encode the information sequence, the receiving end can process the received data accordingly to reliably recover the original information sequence. The encoding method must be visible to both the transmitting and receiving ends. Generally, the encoding method is based on forward error correction (FEC) coding, also known as channel coding. FEC adds redundant information to the information sequence. The receiving end can use this redundant information to reliably recover the original information sequence.

[0060] Some common FEC codes include convolutional codes, Turbo codes, Low Density Parity Check (LDPC) codes, and Polar codes. In FEC encoding, an information sequence with k bits is FEC-encoded to obtain an n-bit FEC codeword (with nk redundant bits), and the FEC code rate is k / n. Convolutional coding can easily encode blocks of arbitrary sizes, and Turbo coding, by utilizing two coded components that operate on the information sequence and by employing interleaving methods that support different code sizes, can support different information sequence sizes.

[0061] LDPC codes are linear block codes that can be defined using a very sparse parity check matrix or a bipartite graph. It is precisely the sparsity of its parity check matrix that enables low-complexity encoding and decoding, thus making LDPC codes practical. Through various practical and theoretical proofs, LDPC codes have demonstrated to be the best-performing channel code in Additive White Gaussian Noise (AWGN) channels, with performance very close to the Shannon limit and superior to convolutional codes and Turbo codes.

[0062] The data channel of the 5G NR mobile communication system adopts quasi-cyclic LDPC coding. Because quasi-cyclic LDPC coding is very simple to describe and has a simple decoder structure, it is used in various communication standards. Quasi-cyclic LDPC coding can also be called structured LDPC coding. Its binary parity check matrix H is an mb×Zc row and nb×Zc column matrix, composed of mb×nb block matrices. Each block matrix is ​​a different power of a basic permutation matrix of size Zc×Zc, which is obtained by right-circular shifting (or left-circular shifting 1) a unit matrix by 1 bit; alternatively, each block matrix can be considered as a submatrix obtained by right-circular shifting (or left-circular shifting) a Zc×Zc identity matrix by several bits. For a binary parity check matrix H, if each Zc×Zc is replaced with an element "0" or an element "1", the zero-block matrix is ​​replaced with "0", and the cyclic shift block matrix of the identity matrix is ​​replaced with "1", the corresponding matrix is ​​called the base graph, but the specific shift values ​​are not distinguished. The base graph is an intermediate product of the design of the QC-LDPC parity check matrix. At this point, as long as the cyclic shift values ​​and the submatrix size are known, a quasi-cyclic LDPC code can be determined. All shift values ​​corresponding to each submatrix constitute an mb×nb matrix, which can be called the base matrix Hb, the shift coefficient parity check matrix, or the parity check matrix of the base graph. The submatrix size Zc can be called the expansion factor, the lift size, or the submatrix size; here, it is described as the lift size. Because the quasi-cyclic LDPC code is very compact and simple in structure, and is very beneficial for decoder implementation, it is also called a structured LDPC code.

[0063] Since quasi-cyclic LDPC codewords are systematic codes, meaning the systematic bits in the codeword are equal to the information bits before encoding, only the parity bits need to be calculated in quasi-cyclic LDPC encoding. Quasi-cyclic LDPC encoding can then be performed based on the parity check matrix described above. For example, the parity check matrix H can be described as two parts: H = [Hs; Hp], where Hs corresponds to the systematic bit matrix and Hp corresponds to the parity bit matrix. According to the LDPC encoding principle, for a quasi-cyclic LDPC codeword C (including the systematic bits Cs and the parity bits Cp), the condition H × C = 0 is satisfied, i.e., [Hs; Hp] × [Cs; Cp] = 0; therefore, it can be deduced that Hs × Cs = Hp × Cp, and thus Cp = (Hp) / (Hp). -1 ×Hs×Cs, where '×' in the formula is binary matrix multiplication and (x)-1 is binary matrix inversion; thus, the parity bit Cp of the quasi-cyclic LDPC codeword can be calculated, thereby obtaining the quasi-cyclic LDPC codeword C=[Cs;Cp].

[0064] Polar codes are a recently proposed type of linear block code. They were proposed by Professor Erdal Arikan in 2009. Polar codes are rigorously constructed codes for Binary Discrete Symmetric Channels (BSCs), achieving the channel capacity of BSCs. The construction and coding principles of polar codes have significant theoretical implications in information theory, pointing the way for code design efforts. The basic idea of ​​polar codes is to utilize the polarization phenomenon of channels, placing bits carrying more information in an "ideal channel" for transmission, while placing known bits ("frozen bits") in a "non-ideal channel." Channel polarization is a ubiquitous phenomenon, widely present not only in BSC channels but also in AWGN channels. It becomes more pronounced with increasing code length. In 2016, polar codes were adopted by the 5G standard as a control channel coding scheme.

[0065] Modulation refers to the process of transmitting information onto a signal suitable for a channel. Modulation generally includes baseband mapping and quadrature modulation. Baseband mapping is the process of mapping a binary bit stream onto a constellation diagram under various modulation methods; while quadrature modulation is the process of shifting the baseband channel onto a carrier wave, which is a spectrum shifting process. Here, modulation mainly refers to baseband mapping. Commonly used modulation methods include BPSK, QPSK, MQAM, and MAPSK.

[0066] At the transmitting end, the transport block to be transmitted needs to be segmented into multiple smaller transport blocks. Then, each of these smaller transport blocks undergoes FEC coding. The transport block to be transmitted has a certain transport block size (TBS) and coding rate. The FEC coding rate is generally defined as the ratio of the number of bits in the original information bit sequence entering the encoder to the number of bits in the actual transmitted bit sequence (or rate-matched output sequence). In 4G LTE and 5G NR communication systems, the transport block size is relatively flexible, thus meeting the various data packet size requirements of mobile communication systems. Furthermore, 4G and 5G communication systems use a modulation and coding scheme (MCS) index to indicate different combinations of modulation order and coding rate R. The TBS index is determined through control information such as downlink control information (DCI) or channel quality indication (CQI), and the size of the actual information bit sequence is determined jointly based on the number of resource blocks (RBs) and the TBS index. Channel types can include data channels and control channels. Data channels generally carry data from user equipment (UE), while control channels carry control information, including MCS index number, channel information, DCI, CQI, and other control information. Bandwidth generally refers to the spectrum width allocated by the system for data transmission. Data transmission directions include uplink data and downlink data. Uplink data generally refers to data transmitted from the UE to the base station, while downlink data refers to data transmitted from the base station to the UE.

[0067] Physical channel mapping refers to mapping modulation symbols onto physical channel resources, such as the spreading code channel in a CDMA system or a subchannel or resource block (composed of multiple subcarriers) in an OFDM system.

[0068] Hybrid Automatic Repeat Request (HARQ) is a crucial link adaptation technology in digital communication systems. The implementation process is as follows: the receiver decodes the received HARQ data packets. If the decoding is correct, it sends an ACK (Acknowledgement) message to the sender, instructing the sender to transmit a new HARQ data packet. If decoding fails, it sends a NACK (Negative Acknowledgement) message to the sender, requesting the sender to retransmit the HARQ data packet. By performing incremental redundancy (IR) or Chase merging decoding on the retransmitted data packets, the receiver can improve the success rate of decoding, achieving high reliability requirements for link transmission.

[0069] Long Term Evolution (LTE) is a 4G (Fourth Generation) wireless cellular communication technology. LTE employs OFDM (Orthogonal Frequency Division Multiplexing) technology, where subcarriers and OFDM symbols constitute the physical time-frequency resources of the LTE system. OFDM technology is currently widely used in wireless communication. Due to the use of a cyclic prefix (CP), CP-OFDM (Cyclic Prefix Orthogonal Frequency Division Multiplexing) systems effectively address multipath delay issues and divide frequency-selective channels into a set of parallel, flat channels. This significantly simplifies channel estimation methods and provides high channel estimation accuracy. DFT-S-OFDM (Discrete Fourier Transform-spread OFDM) is a digital waveform, also known as DFT-spread OFDM, DFT-precoded OFDM, or Transform Precoding, which can be used to transmit data over wide RF channels. This technology is actually a combination of two different technologies: Discrete Fourier Transform (DFT) and Orthogonal Frequency Division Multiplexing (OFDM), added before the IFFT module. It's an orthogonal frequency division multiplexing form used in advanced wireless systems to reduce PAPR (Power Amplifier Performance Rate), allowing power amplifiers to operate more efficiently. In 4G, the uplink waveform is DFTS-OFDM, and the downlink waveform is CP-OFDM. In 5G (Fifth Generation) wireless cellular communication technology, the uplink supports both CP-OFDM and DFTS-OFDM waveforms, while the downlink only supports CP-OFDM. DFT precoding, also known as transform precoding, achieves semi-static switching between the two waveforms by enabling or disabling the transformprecoder's higher-layer configuration signaling.

[0070] In wireless communication networks, transmitters can encode information data according to specific error correction and decoding schemes to improve communication reliability. Transmitters can then modulate the encoded information onto frequency subcarriers for transmission according to specific modulation schemes. Transmitters can use various modulation techniques. In some cases, transmitters may use modulation techniques based on Quadrature Amplitude Modulation (QAM). Modulation schemes can have specific constellation diagrams, with constellation points located in the complex plane. Constellation points can also be called constellation symbols or modulation symbols. Transmissions generated using a specific modulation scheme can carry information data bits represented by constellation symbols, which come from a set of constellation symbols defined for that modulation scheme.

[0071] QAM (Quadrature Amplitude Modulation) is a modulation method that modulates amplitude on two orthogonal carriers. These two carriers are typically sine waves with a phase difference of 90 degrees (π / 2), hence the name "quadrature carriers." The modulation method is named after this. QAM is a widely used modulation technique in digital communication. The transmission characteristics of QAM signals can be intuitively understood through the representation of constellation diagrams. In a constellation diagram, each constellation point corresponds to a specific value in the transmitted signal set. These points are usually arranged in a square grid with equal spacing in the horizontal and vertical directions, forming a two-dimensional geometric figure that facilitates observation of signal distribution. In digital communication, data is usually represented using binary numbers, so the number of constellation points is often a power of 2. As the number of constellation points increases, the amount of information that each symbol can transmit also increases. However, if the average energy of the constellation diagram remains constant, increasing the number of constellation points will lead to a decrease in the distance between the constellation points. In this case, interference between signals will increase, thereby increasing the bit error rate and reducing communication reliability.

[0072] Traditional modulation methods (such as QAM and PSK) use uniformly distributed signal points on the constellation diagram, but this method is not always optimal. Channel capacity generally refers to the maximum transmission rate of a channel, derived from the bandwidth and signal-to-noise ratio (SNR) it supports. This channel capacity is often referred to as "Shannon capacity." QAM-based transmission using uniformly distributed QAM symbols may not achieve Shannon capacity. For example, uniform QAM can asymptotically approach the capacity SNR curve by about 1.53 dB. However, in practical communication channels, according to Shannon theory, signals with a Gaussian distribution are closer to the optimal power distribution, resulting in data transmission rates closer to Shannon capacity, reducing average power, and improving spectral efficiency. Typically, shaping modulation mainly includes two categories: geometric shaping (GS) and probabilistic shaping (PS). In geometric constellation shaping, each constellation point in the complex plane appears with approximately equal probability, but the positions of these points are adjusted to make the signal amplitude distribution closer to a Gaussian distribution, reducing the frequency of high-energy symbols. In terms of constellation diagram form, the smaller the amplitude, the denser the constellation points; the larger the amplitude, the sparser the points. In probabilistic constellation shaping (also known as probabilistic amplitude shaping (PAS)), a more traditional (e.g., grid-like) symbol distribution is used in the complex plane, but the probabilities of using the corresponding constellation symbols are not equal. In this method, each symbol of the input signal is mapped to a point in the constellation diagram, and by adjusting the emission probabilities of each point in the constellation diagram, the signal probability distribution is made closer to the target probability distribution.

[0073] In some respects, a distribution matcher (DM) can be applied to transform a sequence of k uniformly distributed bit sequences (e.g., information bits) into a sequence of n symbols (codewords) with a desired or target probability distribution. An example of a DM is the Constant Component Distribution Matcher (CCDM). A characteristic of CCDM is that all symbol sequences in the CCDM output have the same component (a single component). A component is an ordered set of occurrences of each symbol in a set of M symbols from which the symbols in the DM output sequence originate. When applying DM to constellation shaping, the set of M symbols can be based on a modulation scheme. For example, the set of M modulation symbols or modulation symbol letters for 16-QAM is {±1, ±3}. As another example, the set of M modulation symbols or modulation symbol letters for 64-QAM is {±1, ±3, ±5, ±7}. Therefore, in the context of constellation shaping, a component can also be referred to as a modulation symbol distribution, which may include the number of occurrences of each symbol in the set of M symbols associated with the modulation scheme. While CCDM can provide constellations or shapes with non-uniform distributions, it may not handle short data packets well due to the use of a single component. Therefore, the rate loss may be even greater when using CCDM for short-distance packet transmission.

[0074] HARQ is a crucial link adaptation technology in digital communication systems. The implementation process is as follows: the receiver decodes the received HARQ data packets. If the decoding is correct, it sends an ACK (Acknowledgement) message to the sender, instructing the sender to transmit a new HARQ data packet. If decoding fails, it sends a NACK (Negative Acknowledgement) message to the sender, requesting retransmission of the HARQ data packet. By performing IR or Chase merging decoding on the retransmitted data packets, the receiver can improve the success rate of decoding, thus achieving high reliability in link transmission.

[0075] CBG (Code Block Group) HARQ is a mechanism that optimizes HARQ (Hybrid Automatic Repeat Request). By dividing a transport block (TB) into multiple code block groups (CBGs), it allows retransmission of only the erroneous CBG instead of the entire TB, thereby improving spectral efficiency and transmission reliability. Compared to traditional LTE's TB-level retransmissions, CBG-based HARQ reduces redundant data retransmissions, making it suitable for eMBB (extra-bandwidth services) and URLLC (ultra-low latency communication). Furthermore, it allows for flexible adjustment of the number of CBGs through dynamic configuration (RRC / DCI) to adapt to different channel conditions and service requirements, significantly improving the throughput and resource utilization of 5G systems.

[0076] For CBG HARQ, the DCI dynamically supports CBG transmission through formats such as Format 1_1. Key fields include CBGTI (Coded Block Group Transmission Indicator, the number of bits equals the configured number of CBGs, marking newly transmitted data), CBGFI (Coded Block Group Refresh Indicator, 1 bit controls the HARQ buffer), and HARQ process number and RV (redundancy version). The base station pre-configures maxCodeBlockGroupsPerTransportBlock (e.g., groups 2 / 4 / 8) through RRC and flexibly specifies the CBGs to be transmitted or retransmitted in the DCI (e.g., 4-bit CBGTI "1101" indicates that the third CBG is not sent). The UE then feeds back HARQ-ACK / NACK at the CBG granularity. This mechanism significantly optimizes retransmission efficiency in eMBB high-traffic and URLLC low-latency scenarios, but it increases DCI overhead and depends on the UE's CBG parsing capabilities.

[0077] For CBG HARQ, Downlink Control Information (UCI) supports fine-grained retransmission control through a CBG-based HARQ-ACK mechanism. The UE generates a bitmap based on the number of received CBGs (e.g., 4 CBGs correspond to 4 bits "1011", where each bit explicitly indicates the ACK / NACK status of the corresponding CBG), and provides feedback via PUCCH (short / long format) or PUSCH. This mechanism dynamically coordinates with DCI's CBGTI (Transmission Indicator) and CBGFI (Refresh Indicator) to optimize performance in eMBB (reduced retransmissions) and URLLC (reduced latency), but it increases UCI overhead (e.g., 8 CBGs require an 8-bit complete bitmap) and relies on strict timing synchronization (e.g., fixed PUCCH feedback slots). Bitmap design must balance feedback overhead and latency requirements while ensuring retransmission accuracy.

[0078] For 4G and 5G CP-OFDM or DFTS-OFDM systems, a resource grid consists of (number of RBs * number of subcarriers per RB) subcarriers in the frequency domain and N OFDM symbols in the time domain. For each antenna port p, for each subcarrier spacing configuration, and for each transmission direction (uplink or downlink), there is one resource grid (time-frequency resource grid). Figure 1 This is a schematic diagram of a resource grid implementation provided by existing technology, such as... Figure 1 As shown.

[0079] 5G resource grid single Figure 1At first glance, it looks very similar to the resource grid of 4G. However, the physical dimensions of 5G vary greatly depending on the numbering system. For example, these dimensions can include subcarrier spacing, the number of OFDM symbols in each radio frame, and so on.

[0080] The following section introduces resource elements (REs). Each cell in the resource grid is called an RE, which is the smallest unit of frequency resource for transmission. Similar to 4G, an RE occupies one OFDM symbol in the time domain and one subcarrier in the frequency domain.

[0081] The following section introduces Resource Blocks (RBs). An RB is the smallest unit of resource allocation and a two-dimensional time-frequency concept. Similar to 4G, the 5G protocol defines an RB as containing 12 subcarriers in the frequency domain. However, unlike 4G where the bandwidth of an RB is fixed at 15 * 12 = 180 kHz, in NR, the size of the RB frequency domain resource varies for different subcarrier intervals.

[0082] The following is an introduction to the Resource Block Group (RBG). The RBG is the basic scheduling unit for data channel resource allocation. It is used for resource allocation type 0 to reduce control channel overhead. In the frequency domain, it can be divided into {2, 4, 8, 16} RBs.

[0083] The detailed descriptions illustrated in the accompanying figures are intended as a description of various configurations and not as representing the only configuration in which the concepts described herein can be implemented. The detailed descriptions include specific details to provide a comprehensive understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0084] The method provided in this application can be applied to various communication systems. For example, the communication system can be a long-term evolution (LTE) system, a 5th generation (5G) communication system, a 5G-A communication system, a Wi-Fi system, a 3rd generation partnership project (3GPP) related communication system, a future evolution communication system (such as a 6th generation (6G) or a 7th generation (7G) communication system), or a system integrating multiple systems, etc., without limitation. The following examples illustrate this. Figure 2Taking the communication system 100 shown as an example, the method provided in the embodiments of this application will be described. Figure 2 This is merely an illustrative diagram and does not constitute a limitation on the applicable scenarios of the technical solutions provided in this application.

[0085] Figure 2 This is a schematic diagram of the architecture of a communication system provided in an embodiment of this application. Figure 2 As shown, the communication system 100 may include one or more network devices (i.e., base stations) and one or more terminal devices. For example... Figure 2 As shown, the communication system 100 may include a base station 110, terminal equipment 120, terminal equipment 130, terminal equipment 140, and a core network 150. It should be noted that network equipment refers to the base station.

[0086] Network device 110 can provide communication services to terminal devices 120, 130, and 140, and can also connect to the core network 150. For example, network device 110 communicates with terminal device 120 via a wireless network. When terminal device 120 sends data, the wireless communication module can encode the information for transmission. Specifically, the wireless communication module can acquire a certain number of information bits to be transmitted to access network device 110 through the channel. These information bits may be generated by the processing module, received from other devices, or stored in the storage module. These information bits may be contained in one or more TBs, and TBs can be segmented to generate multiple CBs.

[0087] When the transmission direction of the communication system 100 is uplink, the terminal device 120 is the transmitter and the access network device 110 is the receiver. When the transmission direction of the communication system 100 is downlink, the access network device 110 is the transmitter and the terminal device 120 is the receiver.

[0088] The technical solutions provided in this application can be applied to various wireless communication systems. For example, the technical solutions provided in this application are mainly applied to future communication systems, such as sixth-generation mobile communication systems, next-generation wireless local area network systems, etc. The 6G mobile communication system described in this application includes non-standalone (NSA) 6G mobile communication systems and / or standalone (SA) 6G mobile communication systems.

[0089] The method proposed in this optional embodiment can be used in next-generation mobile communication systems or other wireless communication systems. The data transmission direction is either from the base station to the mobile user (downlink transmission service data) or from the mobile user to the base station (uplink transmission service data). Mobile users include: mobile devices, access terminals, user terminals, user stations, user units, mobile stations, remote stations, remote terminals, user agents, user equipment, user devices, or other terms. Base stations include access points (APs), or may be referred to as node B, radio network controller (RNC), evolved Node B (eNB), base station controller (BSC), base transceiver station (BTS), base station (BS), transceiver function (TF), radio router, radio transceiver, basic service unit, extended service unit, radio base station (RBS), or other terms.

[0090] Base stations can provide communication coverage for macro cells, pico cells, femto cells, and / or other types of cells. A macro cell can cover a relatively large geographic area (e.g., a radius of several kilometers) and can allow unrestricted access for UEs with a service subscription. A pico cell may cover a relatively small geographic area and may allow unrestricted access for UEs with a service subscription. A femto cell can cover a relatively small geographic area (e.g., a home) and can allow restricted access for UEs associated with the femto cell (e.g., UEs in a Closed Subscriber Group (CSG)). The ABS of a macro cell can be referred to as a macro BS. The BS of a pico cell can be referred to as a pico BS. The BS used for a femto cell may be referred to as a femto BS or a home BS. The terms “eNB,” “base station,” “NR BS,” “gNB,” “TRP,” “AP,” “Node B,” “5G NB,” “hNB,” “6G NB,” “iNB,” “7G NB,” and “cell” are used interchangeably here.

[0091] A network controller can be coupled to one or more (e.g., a group of) business units (BSs) and can provide coordination and control for these BSs. The network controller can communicate with the BSs via backhaul. BSs can also communicate with each other, for example, directly or indirectly via wireless or wired backhaul.

[0092] UEs can be distributed throughout the wireless network, and each UE can be fixed or mobile. A UE can communicate with one or more BSs in the wireless network.

[0093] UE can also be referred to as access terminal, terminal, mobile station, user unit, station, etc. UE can be a cellular phone (e.g., smartphone), personal digital assistant (PDA), wireless modem, wireless communication device, handheld device, laptop, cordless phone, wireless local loop (WLL) station, tablet computer, camera, gaming device, netbook, smartbook, ultrabook, medical device or equipment, biometric sensor / device, wearable device (smartwatch, smart clothing, smart glasses, smart wristband, smart jewelry (e.g., smart ring, smart bracelet)), entertainment device (e.g., music or video device or satellite radio), vehicle component or sensor, smart meter / sensor, industrial manufacturing equipment, GPS device, or any other suitable device configured to communicate via wireless or wired media.

[0094] In 5G mobile communication systems, the CSI feedback from the terminal to the base station supports both implicit CSI feedback and feedback based on channel reciprocity. Implicit feedback quantifies information such as CQI / PMI / RI / CRI and feeds it back. Due to different accuracy requirements for feedback between SU ​​and MU, NR supports two types of codebooks for CSI feedback: a standard-precision Type I codebook and a high-precision Type II codebook. Reciprocity-based CSI feedback can be divided into feedback based on full channel reciprocity and feedback based on partial channel reciprocity, depending on the feedback conditions. CSI includes the following measurement information: CQI, PMI, CSI-RS Resource Indication (CRI), SSB Resource Indication (SSBRI), Layer Indication (LI), RI, and L1-RSRP. Among these, SSBRI, LI, and L1-RSRP are new feedback quantities added in 5G compared to 4G. L1 is used to indicate the strongest column in PMI and is used for PT-RS reference signal mapping. SSBRI and L1-RSRP are used for beam management. SSBRI indicates the beam index, and L1-RSRP indicates the beam strength.

[0095] In one embodiment, Figure 3 This is a flowchart illustrating a signal processing method provided in an embodiment of this application. This embodiment is applied to the optimization of link performance for LDPC codes. This embodiment can be executed by a transmitting end. For example, the transmitting end can be a terminal device or a base station. Figure 3 As shown, this embodiment includes: S310-S350.

[0096] S310. Add a CRC bit sequence to the transport block to obtain the transport block after addition.

[0097] S320. Perform code block segmentation and CRC bit sequence addition on the added transmission block in sequence to obtain the code block bit sequence.

[0098] S330. Perform LDPC encoding on each code block bit sequence to obtain the mother codeword.

[0099] S340. Perform bit selection on each mother codeword to obtain the bit selection sequence.

[0100] S350. Perform code block interleaving on each bit selection sequence to obtain a code block interleaving sequence; wherein, determine whether the code block interleaving supports sub-block interleaving based on predefined condition information.

[0101] In one embodiment, each bit selection sequence is subjected to code block interleaving to obtain a code block interleaved sequence, including:

[0102] If code block interleaving supports sub-block interleaving, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain the sub-block interleaved sequence, and the sub-block interleaved sequence is bit interleaved based on the modulation order to obtain the code block interleaved sequence.

[0103] If the code block interleaving does not support sub-block interleaving, bit interleaving is performed on the bit selection sequence based on the modulation order to obtain the code block interleaved sequence.

[0104] In one embodiment, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, including:

[0105] The number of sub-blocks is determined based on the sequence length of the bit selection sequence and the boost value;

[0106] The bit selection sequence is interleaved with sub-blocks according to the number of sub-blocks to obtain the sub-block interleaved sequence.

[0107] In one embodiment, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, including:

[0108] The number of sub-blocks is determined based on the sequence length of the bit selection sequence and the boost value;

[0109] The bit selection sequence is divided into sub-blocks based on the boost value, resulting in multiple sub-blocks;

[0110] Multiple sub-blocks are interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence.

[0111] In one embodiment, the bit selection sequence is divided into sub-blocks based on the boost value to obtain multiple sub-blocks, including:

[0112] The bit selection sequence is divided into sub-blocks in order of the boost value Zc as the sub-block size, resulting in N. sub N sub-blocks; of which Nsub Each sub-block contains N sub-blocks with a length equal to the promotion value Zc. sub -1 code blocks, and the last code block whose sub-block length is less than or equal to the boost value Zc.

[0113] In one embodiment, the sub-block interleaving pattern is a sequence arranged according to a predefined interleaving order, and the number of values ​​of the sub-block interleaving pattern is equal to the number of sub-blocks obtained by sub-block division, or the number of values ​​of the sub-block interleaving pattern is greater than the number of sub-blocks obtained by sub-block division.

[0114] In one embodiment, the sub-block interleaving pattern is composed of 0, 1, 2, ..., N sub -1 is composed of, and N sub The integers are a sequence arranged in a predefined interleaving order.

[0115] In one embodiment, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, including:

[0116] The sequence length E is selected based on the bit selection sequence. r The number of sub-blocks N is determined by the lift value Zc. sub Where r is the code block index;

[0117] The bit selection sequence is divided into sub-blocks based on the lift value Zc to obtain N. sub Each block;

[0118] If the length of the last sub-block is equal to the lift value Zc, then N is processed according to the predefined sub-block interleaving pattern. sub Each sub-block is interleaved to obtain a sub-block interleaved sequence;

[0119] If the length of the last sub-block is less than the lift value Zc, then apply the predefined sub-block interleaving pattern to N excluding the last sub-block. sub -1 sub-blocks are interleaved, and the position of the last sub-block remains unchanged, resulting in a sub-block interleaving sequence.

[0120] In one embodiment, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, including:

[0121] The sequence length E is selected based on the bit selection sequence. r The number of sub-blocks N is determined by the lift value Zc. sub ;

[0122] The bit selection sequence is divided into sub-blocks based on the lift value Zc to obtain N. sub Each block;

[0123] According to the predefined sub-block interleaving pattern, N is processed... subEach sub-block is interleaved to obtain a sub-block interleaving sequence; where the sub-block interleaving pattern consists of 0, 1, 2, ..., N. sub -1 is composed of, and N sub The integers are arranged in a predefined interleaving order, and the last number in the sub-block interleaving pattern is N. sub -1.

[0124] In one embodiment, between sub-block partitioning and sub-block interleaving, if the length of the last sub-block among all sub-blocks after sub-block partitioning is less than the boost value, the last sub-block is bit-padded so that the length of the last sub-block is equal to the boost value.

[0125] In one embodiment, before sub-block partitioning, if the rate-matched length of each code block is not an integer multiple of the boost value, bit padding is performed on the rate-matched sequence of each code block, adding Zc*ceil(E) r / Zc)-E r Fill in bits such that the bit-filled sequence is an integer multiple of the boost value.

[0126] In one embodiment, bit stuffing of the last sub-block includes one of the following:

[0127] Fill the last sub-block with Zc*ceil(E) r / Zc)-E r There are placeholders, where ceil indicates rounding up;

[0128] Fill the last sub-block with Zc*ceil(E) r / Zc)-E r One empty bit symbol.

[0129] In one embodiment, multiple sub-blocks are interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence, including:

[0130] Sub-blocks of size 'lift' are interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence.

[0131] In one embodiment, after performing sub-block interleaving on multiple sub-blocks according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence, the method further includes:

[0132] Remove padding bits contained in the sub-block interleaving sequence.

[0133] In one embodiment, each bit selection sequence is subjected to code block interleaving to obtain a code block interleaved sequence, including:

[0134] If the code block interleaving supports sub-block interleaving, the input index sequence of the corresponding bit selection sequence is interleaved based on the number of sub-blocks to obtain the first interleaving index, and bit interleaving is performed on the first interleaving index based on the modulation order to obtain the second interleaving index. The bit selection sequence is then mapped bit by bit according to the second interleaving index.

[0135] If the code block interleaving does not support sub-block interleaving, bit interleaving is performed on the input index sequence of the corresponding bit selection sequence based on the modulation order to obtain the third interleaving index, and bit-by-bit interleaving mapping is performed on the bit selection sequence according to the third interleaving index.

[0136] In one embodiment, each bit selection sequence is subjected to code block interleaving to obtain a code block interleaved sequence, including:

[0137] If the code block interleaving supports sub-block interleaving, the bit selection sequence is interleaved according to the second interleaving index to obtain the code block interleaving sequence; wherein, the second interleaving index is determined according to the sub-block interleaving based on the first interleaving index, the boost value and the sub-block interleaving pattern, the first interleaving index is determined according to the bit interleaving based on the modulation order, and the second interleaving index is a first function of the output index of the code block interleaving sequence;

[0138] If the code block interleaving does not support sub-block interleaving, the bit selection sequence is interleaved according to the third interleaving index to obtain the code block interleaving sequence. The third interleaving index is determined based on the bit interleaving of the modulation order and is a second function of the output index of the code block interleaving sequence.

[0139] In one example, when code block interleaving supports sub-block interleaving, sub-block interleaving is performed on the input index sequence corresponding to the bit selection sequence based on the number of sub-blocks to obtain a first interleaving index, and bit interleaving is performed on the first interleaving index based on the modulation order to obtain a second interleaving index. The bit selection sequence is then mapped bit by bit according to the second interleaving index, which is obtained by function acquisition of the input index of the code block interleaving sequence.

[0140] When code block interleaving supports sub-block interleaving, code block interleaving is performed on the bit selection sequence according to the second interleaving index to obtain the code block interleaving sequence; wherein, the second interleaving index is determined based on the sub-block interleaving based on the first interleaving index, the boost value and the sub-block interleaving pattern, the first interleaving index is determined based on the bit interleaving based on the modulation order, and the second interleaving index is the first function of the output index of the code block interleaving sequence, which is obtained by performing a function on the output index of the code block interleaving sequence.

[0141] In one example, when code block interleaving does not support sub-block interleaving, bit interleaving is performed on the input index sequence corresponding to the bit selection sequence based on the modulation order to obtain a third interleaving index, and the bit selection sequence is mapped bit by bit according to the third interleaving index. This is a function to obtain the input index of the code block interleaving sequence.

[0142] In the case where code block interleaving does not support sub-block interleaving, code block interleaving is performed on the bit selection sequence according to the third interleaving index to obtain a code block interleaving sequence; wherein, the third interleaving index is determined based on the bit interleaving of the modulation order, and the third interleaving index is the second function of the output index of the code block interleaving sequence, which is obtained by performing a function on the output index of the code block interleaving sequence.

[0143] In one embodiment, before determining the first interleaving index based on the modulation order bit interleaving, the method further includes:

[0144] The bit selection sequence is padded with bits so that the length of each sub-block is equal to the boost value.

[0145] In one embodiment, after performing code block interleaving on the bit selection sequence according to the second interleaving index to obtain the bit interleaved sequence, the method further includes:

[0146] Remove padding bits contained in the sub-block interleaving sequence.

[0147] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0148] It is obtained from the modulation order and the number of sub-blocks corresponding to the transmission block;

[0149] It is obtained from the modulation order, number of sub-blocks and basic graph index corresponding to the transport block.

[0150] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0151] It is determined based on the MCS index of the modulation and coding scheme corresponding to the transport block;

[0152] It is determined based on the MCS index set corresponding to the transport block, wherein the MCS index set includes at least two adjacent MCS indices in an MCS table;

[0153] It is determined based on the MCS index, the MCS index set, and the modulation order corresponding to the transport block;

[0154] It is determined based on the MCS index and transport layer number corresponding to the transport block;

[0155] It is determined based on the MCS index corresponding to the transport block, the transport layer number, and the number of resource elements in each transport block.

[0156] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0157] It is determined based on the coding rate, coding rate range, and modulation order of the transport block;

[0158] It is determined based on the current transmission redundancy version corresponding to the transmission block;

[0159] It is determined based on the current transmission redundancy version corresponding to the transport block, the system bit puncturing situation, the modulation order, and the coding rate.

[0160] In one embodiment, the predefined condition information includes at least one of the following: modulation order, sequence length of bit selection sequence and boost value; code rate and preset code rate threshold; code rate, preset code rate threshold and modulation order; modulation order and preset set of modulation order parameters for supporting sub-block interleaving; preset set of parameters for code rate and modulation order and preset code rate threshold.

[0161] In one embodiment, the predefined condition information includes at least one of the following: higher-level configuration signaling and MCS index of the MCS table; higher-level configuration signaling, MCS index, first preset MCS index set and second preset MCS index set of the MCS table; number of code blocks; number of code blocks and preset code block number threshold; transport block size; transport block size and preset transport block size threshold.

[0162] In one embodiment, the predefined condition information includes at least one of the following: higher-layer configuration enable signaling; higher-layer configuration enable signaling and predefined interleaving enable conditions; control information format; control information format and sub-block interleaving enable conditions; wireless network temporary identifier; search space.

[0163] In one embodiment, the signal processing method further includes:

[0164] The code block interleaving sequence is concatenated to obtain the concatenated codeword sequence.

[0165] In one embodiment, code block concatenation is performed on the code block interleaving sequence to obtain a concatenated codeword sequence, including one of the following:

[0166] The code block interleaving sequence is concatenated in order to obtain the concatenated codeword sequence;

[0167] The code block interleaving sequence is divided into multiple sets of code block interleaving sequences. Each code block interleaving sequence is interleaved and concatenated to obtain the corresponding interleaved and concatenated bit sequences. The interleaved and concatenated bit sequences are then concatenated in sequence to obtain the concatenated codeword sequence.

[0168] In one embodiment, the signal processing method further includes:

[0169] The controlled and multiplexed codeword sequence is scrambled to obtain a scrambled sequence.

[0170] The modulation order of the scrambled sequence is Q. m The modulation mapping yields a sequence of modulation symbols for a codeword stream;

[0171] Map the modulation symbol sequence of the codeword stream to N L There are N transport layers. L Greater than or equal to 1;

[0172] If transform precoding is enabled, for N L The layer modulated symbol sequence is transformed and precoded to obtain N. L Layered complex number symbol sequence;

[0173] Map the complex symbol sequence of each transmission layer to one or more antenna ports;

[0174] Map the complex symbol sequence of each antenna port to a resource element;

[0175] OFDM waveform generation is performed on the complex symbol sequence on the resource unit to obtain the time-domain OFDM waveform.

[0176] In one embodiment, Figure 4 This is a flowchart of another signal processing method provided in an embodiment of this application. This embodiment is applied to the case of optimizing the link performance of LDPC codes. This embodiment can be executed by the transmitting end. Figure 4 As shown, this embodiment includes: S410-S450.

[0177] S410. Add a CRC bit sequence to the transport block to obtain the transport block after addition.

[0178] S420. After adding the transmission block, perform code block segmentation and CRC bit sequence addition in sequence to obtain the code block bit sequence.

[0179] S430. Perform LDPC encoding on each code block bit sequence to obtain the mother codeword.

[0180] S440. Perform bit selection on each mother codeword to obtain the bit selection sequence.

[0181] S450. Perform code block interleaving on each bit selection sequence to obtain a code block interleaving sequence; wherein, determine whether the bit selection supports sub-block interleaving based on predefined condition information.

[0182] In one embodiment, bit selection is performed on each mother codeword to obtain a bit selection sequence, including:

[0183] If bit selection supports sub-block interleaving, bit selection based on bit interleaving is performed on the mother codeword to obtain the bit selection sequence;

[0184] If bit selection does not support sub-block interleaving, bit selection is performed on the mother codeword to obtain the bit selection sequence.

[0185] In one embodiment, bit selection based on bit interleaving is performed on the mother codeword to obtain a bit selection sequence, including:

[0186] Determine the final length E of the bit selection for each code block. r and middle length

[0187] Select from the master codeword One codeword bit;

[0188] right Each codeword bit is interleaved into a sub-block to obtain a sub-block interleaved sequence;

[0189] From length Select E from the sub-block interleaving sequence r Each codeword bit is used as a bit selection sequence.

[0190] In one embodiment, the bit selection final length E r Based on the total number of coded bits G, modulation order Qm, and transmission layer N of the transport block L It has been confirmed.

[0191] In one embodiment, the intermediate length The final length and boost value Z are selected based on the bits. c It has been confirmed.

[0192] In one embodiment, the intermediate length

[0193] In one embodiment, for Each codeword bit is interleaved into sub-blocks to obtain an interleaved sub-block sequence, including:

[0194] Based on the middle length and the increase value Z c Determine the number of sub-blocks N sub ;

[0195] Based on the lift value Z c For the middle length The codeword bits are divided into sub-blocks to obtain N. sub Each block;

[0196] According to the predefined sub-block interleaving pattern, N is processed... sub Each sub-block is interleaved to obtain a sub-block interleaved sequence.

[0197] In one embodiment, based on the boost value Z c For the middle length The codeword bits are divided into sub-blocks to obtain N. sub Each sub-block includes:

[0198] With the increase value Z c For the order of sub-block size, adjust the middle length The codeword bits are divided into sub-blocks to obtain N. sub There are 10 sub-blocks; the length of each sub-block is equal to the lift value Z. c .

[0199] In one embodiment, the sub-block interleaving pattern is composed of 0, 1, 2, ..., N sub -1 is composed of, and N sub The integers are a sequence arranged in a predefined interleaving order.

[0200] In one embodiment, sub-block interleaving involves interleaving all sub-blocks according to a predefined sub-block interleaving pattern.

[0201] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0202] It is obtained from the modulation order and the number of sub-blocks corresponding to the transmission block;

[0203] It is obtained from the modulation order, number of sub-blocks and basic graph index corresponding to the transport block.

[0204] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0205] It is determined based on the MCS index of the modulation and coding scheme corresponding to the transport block;

[0206] It is determined based on the MCS index set corresponding to the transport block, wherein the MCS index set includes at least two adjacent MCS indices in an MCS table;

[0207] It is determined based on the MCS index, the MCS index set, and the modulation order corresponding to the transport block;

[0208] It is determined based on the MCS index and transport layer number corresponding to the transport block;

[0209] It is determined based on the MCS index corresponding to the transport block, the transport layer number, and the number of resource elements in each transport block.

[0210] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0211] It is determined based on the coding rate, coding rate range, and modulation order of the transport block;

[0212] It is determined based on the current transmission redundancy version corresponding to the transmission block;

[0213] It is determined based on the current transmission redundancy version corresponding to the transport block, the system bit puncturing situation, the modulation order, and the coding rate.

[0214] In one embodiment, the predefined condition information includes at least one of the following: modulation order, sequence length of bit selection sequence and boost value; code rate and preset code rate threshold; code rate, preset code rate threshold and modulation order; modulation order and preset set of modulation order parameters for supporting sub-block interleaving; preset set of parameters for code rate and modulation order and preset code rate threshold.

[0215] In one embodiment, the predefined condition information includes at least one of the following: higher-level configuration signaling and MCS index of the MCS table; higher-level configuration signaling, MCS index, first preset MCS index set and second preset MCS index set of the MCS table; number of code blocks; number of code blocks and preset code block number threshold; transport block size; transport block size and preset transport block size threshold.

[0216] In one embodiment, the predefined condition information includes at least one of the following: higher-layer configuration enable signaling; higher-layer configuration enable signaling and predefined interleaving enable conditions; control information format; control information format and sub-block interleaving enable conditions; wireless network temporary identifier; search space.

[0217] In one embodiment, the signal processing method further includes:

[0218] The code block interleaving sequence is concatenated to obtain the concatenated codeword sequence.

[0219] In one embodiment, code block concatenation is performed on the code block interleaving sequence to obtain a concatenated codeword sequence, including one of the following:

[0220] The code block interleaving sequence is concatenated in order to obtain the concatenated codeword sequence;

[0221] The code block interleaving sequence is divided into multiple sets of code block interleaving sequences. Each code block interleaving sequence is interleaved and concatenated to obtain the corresponding interleaved and concatenated bit sequences. The interleaved and concatenated bit sequences are then concatenated in sequence to obtain the concatenated codeword sequence.

[0222] In one embodiment, the signal processing method further includes: scrambling the control and multiplexed codeword sequence to obtain a scrambled sequence; and modulating the scrambled sequence with a modulation order of Q. m The modulation mapping is performed to obtain a modulation symbol sequence of a codeword stream; the modulation symbol sequence of the codeword stream is then mapped to N. L There are N transport layers.L Greater than or equal to 1; if transform precoding is enabled, for N L The layer modulated symbol sequence is transformed and precoded to obtain N. L Layer complex symbol sequence; map the complex symbol sequence of each transmission layer to one or more antenna ports; map the complex symbol sequence of each antenna port to resource elements; generate OFDM waveforms from the complex symbol sequences on the resource elements to obtain time-domain OFDM waveforms.

[0223] Preferred embodiment 1

[0224] According to one aspect of this optional embodiment, the signal processing method provided by this optional embodiment can be applied to the transmitting communication equipment of next-generation 6G communication systems and subsequent communication systems (6G and beyond), such as base station or terminal or relay station or satellite communication equipment, or the transmitting communication equipment of next-generation fixed access wireless communication systems, such as AP or terminal.

[0225] Figure 5 This is a flowchart of another signal processing method provided in the embodiments of this application, applied to the transmitting end. Figure 5 The device executing the given signal processing method is a transmitter. The signal processing method includes at least one of the following steps:

[0226] Step S501, CRC addition to transport block: Calculate the CRC check bit sequence based on the given CRC (Cyclic Redundancy Check) polynomial and the input transport block sequence, and add the generated CRC check bit sequence to the end of the transport block to obtain the transport block after addition.

[0227] Step S502, code block segmentation and code block CRC addition: Determine the number of code blocks C b If the number of code blocks C b If the value is greater than 1, the input data sequence is segmented into code blocks, and a CRC is added to the segmented code blocks or code block groups to obtain the code block bit sequence.

[0228] Optionally, a block CRC can be added to each segmented block.

[0229] Optionally, the number of code blocks after segmentation is C. b One, will C b Each segment of the code block is divided into Mc groups, and a code block group CRC is added to each group. The code block group CRC is generated based on the data of the group and a CRC generator polynomial encoding, where Mc is a positive integer greater than or equal to 1.

[0230] There is an alternative to the above S502, which only involves code block segmentation and does not involve adding code block CRC.

[0231] Step S503, Channel coding: For C b Each code block sequence in the input code block bit sequence is individually channel-coded to generate C. b A number of lengths N r The mother codeword.

[0232] Furthermore, the information bit sequence encoded by the input channel is After channel coding, the sequence corresponding to the mother codeword is obtained as follows:

[0233] Furthermore, the channel coding is either LDPC code or Polar code.

[0234] Furthermore, r is the code block index, r = 0, ..., C b -1.

[0235] Furthermore, here is an example where channel coding uses the basic graph matrix (BG1 and BG2) of 5G NR and its parity check matrix.

[0236] Step S504, Bit selection: for C b A number of lengths N r The length of each channel encoded in the mother codeword is N. r The mother codeword is individually bit-selected to obtain C. b A length of E r The sequence after bit selection is used as the bit selection sequence.

[0237] Furthermore, r is the code block index, r = 0, ..., C b -1.

[0238] Specifically, each channel is first encoded to a length of N. r The mother codewords are written separately, each with a length of N. cb In the circular buffer, E is then selected individually from each circular buffer based on the redundant version currently being transmitted. r 1 codeword bit, generate C b The sequence after selecting 1 bit. Where E r It is a positive integer greater than 1, E r This refers to the length of the rate-matched output sequence of the r-th code block, where r is the code block index, r = 0, 1, ..., C. b -1.

[0239] Optionally, if circular cache rate matching is not supported, N cb =min(N) r N ref Otherwise, Ncb =min(N) r N ref ), N ref It is a code length that matches the finite cache rate.

[0240] Optionally, N ref It is determined by the number of code blocks C b The code rate R of a finite circular buffer LBRM The maximum number of antenna layers, maximum code rate, maximum modulation order, maximum number of PRBs, and maximum code rate are determined.

[0241] In one example, codeword bits (bit sequence) are retrieved from the r-th circular buffer. In the process of bit selection, the r-th bit sequence after bit selection is obtained. In one example, the bit selection sequence of the r-th code block is determined based on the redundancy version, and the redundancy version number of the currently transmitted code block is denoted as rv. id ,rv id It can be equal to 0, 1, 2, or 3, r = 0, 1, ..., C b -1. e r The generation process is shown in the following pseudocode:

[0242]

[0243] The starting position k0 is based on the redundant version number rv. id The basic graph matrix index is determined by a preset table. Based on the preset table, different redundant version numbers (rv) are determined. id The different starting positions k0 are based on the BG index and N. cb and Z c Predefined.

[0244] Step S505, Code Block Interleaving: Perform code block interleaving separately on the input sequence of each code block to obtain C. b The interleaved sequence of outputs.

[0245] Furthermore, it is first determined whether sub-block interleaving needs to be supported based on predefined condition information. If sub-block interleaving is supported, the input bit sequence is then processed based on the number of sub-blocks N. sub Sub-block interleaving occurs if necessary, otherwise no sub-block interleaving occurs. Secondly, based on the modulation order Q... m Bit interleaving is performed on the bit sequences after sub-block interleaving. Where, E r Zc is the length of the bit-selected block (also called the sequence length of the bit-selected sequence); Zc is the boost value. Optionally, N sub =ceil(E r / Zc).

[0246] Furthermore, based on the modulation order Q m Bit interleaving is performed on the bit sequence after sub-block interleaving, and the most significant bit (MSB) of the bit selection sequence of each code block is mapped to the high reliability bits of the constellation diagram with modulation order Qm.

[0247] Furthermore, the sub-block interleaving, based on the bit selection length E r The number of sub-blocks N is determined by the lift value Zc. sub =ceil(E r / Zc), then based on the number of sub-blocks N sub Perform sub-block interleaving.

[0248] Furthermore, based on the modulation order Q m Select the bit sequence of the input for each code block. Individually interleaved into an output bit sequence As a code block interleaving sequence.

[0249] Furthermore, the input bit selection sequence can be interleaved into an output bit sequence as a code block interleaving sequence using the following method:

[0250]

[0251] Furthermore, firstly, based on predefined condition information, it is determined whether sub-block interleaving is required for code block interleaving. If sub-block interleaving is supported, then sub-block interleaving is performed on the bit selection sequence of the input for each code block; otherwise, sub-block interleaving is not performed. Secondly, based on the modulation order Q... m The bit sequence after sub-block interleaving (also called the sub-block interleaved sequence) is bit interleaved; finally, based on the modulation order Q... m Bit interleaving is performed on the bit sequence after sub-block interleaving to obtain the final code block interleaved sequence, which is used as the code block interleaving sequence.

[0252] Method 1: N sub Sub-blocks intertwined

[0253] Furthermore, the sub-block interleaving, firstly, is based on the bit selection length E. r The number of sub-blocks N is determined by the lift value Zc. sub Secondly, the input bit selection sequence is divided into sub-blocks based on the boost value Zc to obtain N. sub Each sub-block. Then, the N sub-blocks are interleaved according to a predefined sub-block pattern. sub Sub-blocks are interleaved.

[0254] Furthermore, the sub-block interleaving is first performed based on the bit selection length E. r The number of sub-blocks N is determined by the boost value Zc. sub =ceil(E r / Zc); then, the input bit sequence is divided into sub-blocks in order of the boost value Zc as the sub-block size, to obtain N sub Individual blocks.

[0255] Furthermore, the bit selection sequence is divided into sub-blocks in order of increasing value Zc as the sub-block size, resulting in N. sub N sub-blocks; wherein, the N sub Each sub-block contains N sub-blocks with a length equal to the promotion value Zc. sub -1 code blocks, and the last code block whose sub-block length is less than or equal to the boost value Zc.

[0256] Furthermore, the N sub Each sub-block includes N blocks of length Zc. sub -1 code block and a length E r -(N sub -1)*Zc's 1 code block; then according to the predefined sub-block interleaving pattern, the N sub Each sub-block undergoes sub-block interleaving. Furthermore, the cascaded interleaving of N... sub Individual blocks.

[0257] Furthermore, the sub-block interlacing pattern is composed of 0, 1, 2, ..., N. sub -1 is composed of, and is the N mentioned above. sub A sequence of integers arranged according to a predefined interleaving order. Further, the sub-block interleaving pattern P(i) is composed of 0, 1, 2, ..., N. sub -1 is composed of, and is the N mentioned above. sub A sequence of n integers arranged in a predefined interleaving order, where i ranges from 0 to N. sub -1.

[0258] For example, based on 5G BG1 LDPC, the 256QAM modulation and 1 / 2 code rate sub-block interleaving pattern P(i) designed in this paper is [1,15,22,5,16,62,9,14,61,7,17,52,4,32,11,3,30,6,13,51,19,23,47,63,26,27,2,10,54,41,31,43,20,49,28,64,57,8,39,24,65,36,12,18,40,37,56,58,48,29,46,25,53,45,35,34,66,50,38,33,55,59,60,44,42,21]-1, where i is the element position index of the sequence, N sub =66. It should be noted that the original sequence position index starts from 1, so we need to subtract 1 from each sequence element to make the sequence position index start from 0.

[0259] Method 2: N sub -1 or N sub Sub-blocks intertwined

[0260] Furthermore, the sub-block interleaving, firstly, is based on the bit selection length E. r The number of sub-blocks N is determined by the lift value Zc. sub Secondly, the input bit sequence is divided into sub-blocks based on the boost value Zc to obtain N. sub Then, if the size of the last sub-block is equal to Zc, the N sub-blocks are interleaved according to a predefined sub-block pattern. sub The N sub-blocks are interleaved; if the size of the last sub-block is smaller than Zc, the N sub-blocks are interleaved according to a predefined sub-block interleaving pattern. sub -1 sub-blocks are interleaved, and the last sub-block of the input is used as the last sub-block of the output.

[0261] Furthermore, the N is processed according to a predefined sub-block interleaving pattern. sub -1 sub-blocks are interleaved according to the first N sub-blocks of the predefined interleaving pattern. sub -1 integer pairs of the N sub -1 sub-blocks are interleaved.

[0262] Furthermore, the sub-block interleaving is first performed based on the bit selection length E. r The number of sub-blocks N is determined by the boost value Zc. sub =ceil(E r / Zc); then, the input bit sequence is divided into sub-blocks in order of the boost value Zc as the sub-block size, to obtain N sub N sub-blocks, wherein the N sub Each sub-block includes N blocks of length Zc. sub -1 code block and a length E r -(N sub -1)*Zc's code block; if the last sub-block size is equal to Zc, then the N is interleaved according to the predefined sub-block pattern. sub The N sub-blocks are interleaved; if the size of the last sub-block is smaller than Zc, the N sub-blocks are interleaved according to a predefined sub-block interleaving pattern. sub -1 sub-blocks are interleaved, and the last input sub-block is used as the last output sub-block. Furthermore, the cascaded interleaved N... sub Individual blocks.

[0263] Method 3: N sub -1 sub-block interleaving (i.e., the last sub-block does not participate in interleaving).

[0264] Furthermore, the sub-block interleaving, firstly, is based on the bit selection length E.r The number of sub-blocks N is determined by the lift value Zc. sub Secondly, the input bit sequence is divided into sub-blocks based on the boost value Zc to obtain N. sub Each sub-block. Then, the N sub-blocks are interleaved according to a predefined sub-block pattern. sub Sub-blocks are interleaved; wherein, the sub-block interleaving pattern P(i) is composed of 0, 1, 2, ..., N. sub -1 is composed of, and the N is said to be sub A sequence of integers arranged in a predefined interleaving order, where the last number in the sub-block interleaving pattern is N. sub -1.

[0265] It should be noted that the last number is always N. sub -1 indicates that the last sub-block does not participate in sub-block interleaving, meaning the last sub-block in the input is still the last sub-block in the output. This feature is mainly used to solve the problem of the last sub-block being less than the boost value Zc, which is beneficial for the overall hardware implementation.

[0266] Furthermore, the sub-block interleaving is implemented according to the following pseudocode:

[0267] Let the codeword bits of the interleaved input subblocks be x0, x1, ..., x N-1 The codeword bits for the output sub-block interleaving are y0, y1, ..., y N-1 Where N = N sub *Z c ;

[0268]

[0269] Furthermore, the sub-block interleaving pattern is from 0 to N. sub -1 of N sub A sequence of integers arranged in a predefined interleaving order.

[0270] Furthermore, the aforementioned sub-block interleaving refers to performing sub-block interleaving on all sub-blocks according to a predefined sub-block interleaving pattern.

[0271] Furthermore, after concatenating and interleaving all sub-blocks, the resulting output code block interleaved bit sequence is obtained.

[0272] It should be noted that the technical solution of this application solves the problem of how to support sub-block interleaving when the size of the last sub-block is likely to be smaller than the boost value Zc. On the one hand, it satisfies the actual channel resources for better matching, and on the other hand, it maintains a relatively simple interleaving hardware implementation.

[0273] Alternative to sub-block interleaving 1 – Block interleaving based on padding bits

[0274] Furthermore, between sub-block partitioning and sub-block interleaving, if the last sub-block among all sub-blocks after partitioning is less than the lift value Zc, add one or more placeholders or NULL (also called null bit symbols) to the last sub-block and make the size of the last sub-block equal to the lift value Zc, so that the size of all sub-blocks is Zc after adding them; then perform sub-block interleaving; after sub-block interleaving, remove all added placeholders or NULL.

[0275] Furthermore, firstly, Zc*ceil(E) is added to the bit selection sequence of each code block. r / Zc)-E r A placeholder or NULL bit symbol. Then, proceed with N. sub =ceil(E r Interleaving is performed between sub-blocks of size Zc ( / Zc). After interleaving, all added placeholders or NULL values ​​are removed.

[0276] Furthermore, before sub-block partitioning, if the rate-matched length of each code block is not an integer multiple of the boost value, bit padding is performed on the rate-matched sequence of each code block, adding Zc*ceil(Er / Zc)-Er padding bits to make the bit-padded sequence an integer multiple of the boost value. Even further, N... sub =ceil(E r Interleaving is performed between sub-blocks of size Zc ( / Zc). After interleaving, all added placeholders or NULL values ​​are removed.

[0277] Furthermore, the sub-block interleaving is implemented according to the following pseudocode:

[0278] Let the codeword bits of the interleaved input subblocks be x0, x1, ..., x N-1 The codeword bits for the output sub-block interleaving are y0, y1, ..., y N-1 Where N = N sub *Z c ;

[0279]

[0280]

[0281] Furthermore, after removing the added placeholders or NULL values, all sub-blocks are concatenated to obtain the bit sequence after interleaving the output code block.

[0282] Alternative to sub-block interleaving 2 – Code block interleaving scheme oriented towards input bit index sequence

[0283] If the code block interleaving supports sub-block interleaving.

[0284] Based on the number of sub-blocks N sub Sub-block interleaving is performed on the input bit index sequence corresponding to the bit selection sequence to obtain the first interleaving index;

[0285] The first interleaving index is bit-interleaved based on the modulation order to obtain the second interleaving index;

[0286] The bit selection sequence is mapped bit-by-bit according to the second interleaving index to obtain the code block interleaving output sequence.

[0287] If the code block interleaving does not support sub-block interleaving.

[0288] Based on the modulation order, the input index sequence corresponding to the bit selection sequence is bit interleaved to obtain the third interleaving index;

[0289] The bit selection sequence is mapped bit-by-bit according to the third interleaving index to obtain the code block interleaving output sequence.

[0290] Alternative to sub-block interleaving 3 – Code block interleaving scheme oriented towards output bit index sequence

[0291] If the code block interleaving supports sub-block interleaving.

[0292] Determine the first interleaving index based on the modulation order of the bit interleaving;

[0293] The second interleaving index is determined based on the first interleaving index, the boost value, and the sub-block interleaving pattern;

[0294] The bit selection sequence is interleaved according to the second interleaving index to obtain the interleaved output sequence.

[0295] If the code block interleaving does not support sub-block interleaving.

[0296] Determine the third interleaving index based on the modulation order of bit interleaving;

[0297] The bit selection sequence is interleaved according to the third interleaving index to obtain the interleaved output sequence.

[0298] Furthermore, if code block interleaving supports sub-block interleaving, the code block interleaving includes the following steps:

[0299] Step (1-1) determines the interleaving index k(n) based on the modulation order of bit interleaving.

[0300] Step (1-2) is to determine the interleaving index J(n) based on the interleaving index k(n), the lifting value Zc, and the sub-block interleaving pattern P(i).

[0301] Step (1-3) involves interleaving the input bit sequence according to the interleaving index J(n).

[0302] Furthermore, if code block interleaving supports sub-block interleaving, the following is a pseudocode example to implement the above processing:

[0303] Let the bit sequence of the codeword after bit selection for each input code block be x0, x1, ..., x N-1 The codeword bits for the output sub-block interleaving are y0, y1, ..., y N-1 Where N = E r ;

[0304]

[0305] Furthermore, before step 1, placeholders or null symbols are added to the bit selection sequence of each code block. Optionally, the number of placeholders or null (NULL) bit symbols is Zc*ceil(E r / Zc)-E r .

[0306] Furthermore, after step 3, remove all added placeholders or empty NULLs.

[0307] Furthermore, after removing the added placeholders or NULL values, all sub-blocks are concatenated to obtain the bit sequence after interleaving the output code block.

[0308] Furthermore, the sub-block interleaving pattern P(i) ranges from 0 to N. sub -1 of N sub A sequence of N integers arranged in a predefined interleaving order, with the last number always being N. sub -1.

[0309] It should be noted that the last number is always N. sub -1 indicates that the last sub-block does not participate in sub-block interleaving, meaning the last sub-block in the input is still the last sub-block in the output. This feature is mainly used to solve the problem of the last sub-block being less than the boost value Zc, which is not conducive to the overall hardware implementation.

[0310] It should be noted that this global interleaving scheme, which integrates two-step interleaving, can achieve the function of two-step interleaving in a single interleaving operation by pre-storing the interleaving address J(n), which significantly reduces complexity and processing time latency.

[0311] Method for determining sub-block interlacing patterns

[0312] Furthermore, the sub-block interleaving pattern is based on the modulation order Q corresponding to the transport block. m Number of sub-blocks N subPredefined. Optional, Q m It is 4 or 6. Optionally, Q m It can be 4, 6, or 8. Optionally, Q... m It could be 4, 6, 8, or 10.

[0313] Furthermore, the sub-block interleaving pattern is based on the modulation order Q corresponding to the transport block. m Number of sub-blocks N sub And the basic graph index is predefined. Optionally, Q m It is 4 or 6. Optionally, Q m It can be 4, 6, or 8. Alternatively, Qm can be 4, 6, 8, or 10.

[0314] Furthermore, it supports each modulation order Q of sub-block interleaving. m There is one or more preset sub-block interlacing patterns. Optionally, Qm is 4 or 6. Optionally, Q m It can be 4, 6, or 8. Optionally, Q... m It could be 4, 6, 8, or 10.

[0315] Furthermore, it supports each modulation order Q of sub-block interleaving. m There are multiple preset sub-block interleaving patterns. Optionally, the multiple sub-block interleaving pattern sequences of the same modulation order Qm have different lengths, and the multiple sub-block interleaving patterns have a nesting relationship. Optionally, the nesting relationship means that a short sub-block interleaving pattern sequence is part of a long sub-block interleaving pattern. Optionally, the nesting relationship means that the first equal-length portions of a short sub-block interleaving pattern sequence and a long sub-block interleaving pattern sequence are the same.

[0316] Furthermore, it supports the modulation order Q of sub-block interleaving. m =4 has N Qm＝4 N preset sub-block interlacing patterns Qm＝4 It is a positive integer greater than or equal to 1. Optionally, N Qm＝4 = 1 or 2 or 3 or 4 or 5 or 6.

[0317] Furthermore, it supports the modulation order Q of sub-block interleaving. m =6 has N Qm＝6 N preset sub-block interlacing patterns Qm＝6 It is a positive integer greater than or equal to 1. Optionally, N Qm＝6 = 1 or 2 or 3 or 4 or 5.

[0318] Furthermore, it supports the modulation order Q of sub-block interleaving. m =8 has N Qm＝8 N preset sub-block interlacing patterns Qm＝8 It is a positive integer greater than or equal to 1. Optionally, NQm＝8 = 1 or 2 or 3.

[0319] Furthermore, it supports the modulation order Q of sub-block interleaving. m =10 has N Qm＝10 N preset sub-block interlacing patterns Qm＝8 It is a positive integer greater than or equal to 1. Optionally, N Qm＝10 =1.

[0320] Furthermore, different modulation orders Q m The corresponding sub-block interleaving patterns are different. Optionally, Q m It is 4 or 6. Optionally, Q m It can be 4, 6, or 8. Optionally, Q... m It could be 4, 6, 8, or 10.

[0321] Furthermore, the sub-block interleaving pattern is determined based on the MCS index corresponding to the transport block.

[0322] Furthermore, the sub-block interleaving pattern is determined based on the MCS index set corresponding to the transport block, wherein the MCS index set includes at least two adjacent MCS indices in an MCS table.

[0323] Furthermore, the sub-block interleaving pattern is based on the MCS index, the MCS index set, and the modulation order Q of the transport block. m Certainly. Optionally, at a given modulation order Q m Under the given conditions, the MCS index set to which the current transport block belongs is determined based on the current transport block's MCS index, and then the corresponding interleaving pattern sequence is determined based on the determined MCS index set. Specifically, given a specific modulation order, multiple MCS index sets are predefined, and each MCS index set predefines an interleaving pattern sequence. Furthermore, a subset sequence of the interleaving pattern sequence is determined based on the current transport block's MCS index, serving as the sub-block interleaving pattern for the current transport's sub-block interleaving operation. Optionally, the subset sequence is selected sequentially from the beginning position of the interleaving pattern sequence. As a technical advantage, this method significantly reduces the number of interleaving patterns and the complexity of the interleaver.

[0324] Furthermore, the sub-block interleaving pattern is based on the MCS index corresponding to the transport block and the transport layer number N. L It's confirmed.

[0325] Furthermore, the sub-block interleaving pattern is based on the MCS index corresponding to the transport block and the transport layer number N. L The number N of resource elements allocated to the transport block RE It's confirmed.

[0326] Furthermore, the sub-block interleaving pattern is based on the coding rate, coding rate range, and modulation order Q of the transport block. m Certainly. Optionally, at a given modulation order Q m Under the given conditions, the assigned coding rate interval is determined based on the coding rate of the current transport block, and then the corresponding interleaving pattern sequence is determined based on the determined coding rate interval. Specifically, given a specific modulation order, multiple coding rate intervals are predefined, and each coding rate interval predefines an interleaving pattern sequence. Furthermore, a subset sequence of the interleaving pattern sequence is determined based on the coding rate of the current transport block, serving as the actual sub-block interleaving pattern for the current transport. This subset sequence is selected sequentially from the beginning of the interleaving pattern sequence. As a technical advantage, this method significantly reduces the number of interleaving patterns and the complexity of the interleaver.

[0327] Furthermore, the sub-block interleaving pattern is based on the MCS index, the MCS index set, and the modulation order Q of the transport block. m Certainly. Optionally, at a given modulation order Q m Under the given conditions, the assigned coding rate interval is determined based on the coding rate of the current transport block, and then the corresponding interleaving pattern sequence is determined based on the determined coding rate interval. Specifically, given a specific modulation order, multiple coding rate intervals are predefined, and each coding rate interval predefines an interleaving pattern sequence. Furthermore, a subset sequence of the interleaving pattern sequence is determined based on the coding rate of the current transport block, serving as the actual sub-block interleaving pattern for the current transport. This subset sequence is selected sequentially from the beginning of the interleaving pattern sequence. As a technical advantage, this method significantly reduces the number of interleaving patterns and the complexity of the interleaver.

[0328] Furthermore, the sub-block interleaving pattern is determined based on the redundancy version of the currently transmitted transport block. Optionally, different redundancy versions define different sub-block interleaving patterns. Optionally, the redundancy version is 0, 1, 2, or 3.

[0329] Furthermore, the sub-block interleaving pattern is determined based on the redundancy version, modulation order, and coding rate of the current transmission of the transport block. Optionally, different redundancy versions define different sub-block interleaving patterns. Optionally, the redundancy version is 0, 1, 2, or 3.

[0330] Optionally, under the condition that the current transmission uses the same modulation order Qm and the same code rate Rc, the current transmission uses a first sub-block interleaving pattern when the redundancy version has a first value; the current transmission uses a second sub-block interleaving pattern when the redundancy version has a second value. Wherein, the first value of the redundancy version and the first value of the redundancy version are different, and the first sub-block interleaving pattern sequence and the second sub-block pattern sequence are different. Optionally, the redundancy version is 0, 1, 2, or 3, and L equals Zc or 2*Zc. Wherein, Rc is a real number greater than 0 and less than 1.

[0331] Furthermore, the sub-block interleaving pattern is determined based on whether the current transmission supports puncturing the first L system bits when the redundancy version is 0.

[0332] Furthermore, the sub-block interleaving pattern is determined based on whether the current transmission supports puncturing the first L system bits, modulation order, and coding rate when the redundancy version is 0.

[0333] Optionally, under the condition that the current transmission uses the same modulation order Qm and the same code rate Rc, the current transmission supports puncturing the first L system bits when the redundancy version is 0, and uses the first sub-block interleaving pattern; the current transmission does not support puncturing the first L system bits when the redundancy version is 0, and uses the second sub-block interleaving pattern. The first sub-block interleaving pattern sequence and the second sub-block pattern sequence are different. Optionally, the redundancy version is 0, 1, 2 or 3, and L equals Zc or 2*Zc. Wherein, Rc is a real number greater than 0 and less than 1.

[0334] Figure 6 This is a comparative diagram of performance gain under the same code rate and different modulation orders provided in an embodiment of this application, as shown in the figure. Figure 6 As shown, the modulation order Qm used in the left figure is 8, and the modulation order Qm used in the right figure is 6, and the code rate Rc used in both is 1 / 3.

[0335] like Figure 6 As shown, from a technical perspective, extensive research has revealed that the technical solution of this embodiment can achieve different benefits depending on the circumstances. On the one hand, it can achieve SNR performance gain (between 0.1dB and 0.35dB). On the other hand, since adding sub-block interleavers leads to hardware complexity and latency, its application range is limited according to the code rate and modulation method, thereby greatly reducing the number of interleaving patterns and reducing interleaving complexity.

[0336] Whether sub-block interleaving is supported is determined by a specific method.

[0337] Specific Sub-Example 1

[0338] Furthermore, whether sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information includes the modulation order Qm and the bit selection length E. r And the increase value Zc.

[0339] Furthermore, based on the length E after bit selection r The number of sub-blocks N is determined by the lift value Zc. sub Then, based on the modulation order Qm and the number of sub-blocks N sub Determine if sub-block interleaving is supported. Optionally, N sub =ceil(E r / Zc).

[0340] Furthermore, it is first determined whether the modulation order Qm belongs to the preset set of modulation order parameters supporting sub-block interleaving; if the modulation order Qm does not belong to the preset set of modulation order parameters supporting sub-block interleaving, sub-interleaving is not performed; if the modulation order Qm belongs to the preset set of modulation order parameters supporting sub-block interleaving, the length e after bit selection is determined. r The number of sub-blocks N is determined by the lift value Zc. sub Then, based on the modulation order Qm and the number of sub-blocks N sub Determine if sub-block interleaving is supported. If not, do not perform sub-block interleaving. If it is supported, determine the appropriate sub-block interleaving based on the modulation order Qm and the number of sub-blocks N. sub The sub-block interleaving pattern is obtained by looking up the table and then the sub-blocks are interleaved.

[0341] Specific Sub-Implementation Example 2

[0342] Whether sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information includes the bitrate R and a preset bitrate threshold R0. th (Also known as a preset bit rate threshold). Optionally, the predefined condition information also includes the modulation order Qm.

[0343] Furthermore, if the bit rate R is less than a preset bit rate threshold, sub-block interleaving is performed; if the bit rate R is greater than the preset bit rate threshold, sub-block interleaving is not performed. Here, the bit rate is a real number greater than 0 and less than 1. It should be noted that the terms "greater than" and "less than" can also include two variations: greater than or equal to and less than. Both "greater than" and "less than or equal to" fall within the scope of protection of this application.

[0344] Optionally, the preset bitrate threshold is a real number greater than 0.30 and less than 0.85. Optionally, the preset bitrate threshold is a real number greater than 0.40 and less than 0.75. Optionally, the preset bitrate threshold is a real number greater than 0.45 and less than 0.70. Optionally, the preset bitrate threshold is a real number greater than or equal to 0.50 and less than 0.6. Optionally, the preset bitrate threshold is a real number greater than or equal to 0.50 and less than 0.55. Optionally, the preset bitrate threshold is 1 / 2, 7 / 16, 9 / 16, 5 / 8, or 2 / 3.

[0345] Optionally, the preset code rate threshold is obtained based on the modulation order Qm corresponding to the transport block.

[0346] Optionally, if the first modulation order Qm1 is less than the second modulation order Qm2, the first code rate threshold R corresponding to the first modulation order Qm1 is... th1 The second code rate threshold R is less than the second modulation order Qm2. th2 .

[0347] Optionally, when Qm = 4, the preset threshold R of the bit rate is... th It is a real number greater than or equal to 0.5 and less than or equal to 0.65.

[0348] Optionally, when Qm = 4, the preset threshold R of the bit rate is... th =553 / 1024 or 616 / 1024.

[0349] Optionally, when Qm = 6, the preset threshold R of the bit rate is... th It is a real number that is greater than or equal to 0.55 and less than or equal to 0.675.

[0350] Optionally, when Qm = 6, the preset threshold R of the bit rate is... th = 616 / 1024 or 666 / 1024.

[0351] Optionally, when Qm = 8, the preset threshold R of the bit rate is... th It is a real number greater than or equal to 0.65 and less than or equal to 0.8.

[0352] Optionally, when Qm = 8, the preset threshold R of the bit rate is... th =682.5 / 1024 or 711 / 1024.

[0353] Optionally, when Qm = 10, the preset threshold R of the bit rate is... th = is a real number greater than or equal to 0.75 and less than or equal to 0.85.

[0354] Optionally, when Qm = 10, the preset threshold R of the bit rate is... th =805.5 / 1024.

[0355] It should be noted that one implementation of the bitrate in this application is the target bitrate, and another implementation of the bitrate in this application is the effective bitrate (i.e., the actual bitrate). This concept applies to all content and all embodiments protected in this application.

[0356] Specific Sub-Example 3

[0357] Whether sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information consists of the modulation order Qm and a preset set of modulation order parameters that support sub-block interleaving.

[0358] Furthermore, if the modulation order Qm belongs to the preset set of modulation order parameters that support sub-block interleaving, sub-block interleaving is performed; if the modulation order Qm does not belong to the preset set of modulation order parameters that support sub-block interleaving, sub-interleaving is not performed.

[0359] Preferably, the preset set of modulation order parameters is {4,6}.

[0360] The optional set of modulation order parameters is {4}.

[0361] Optionally, the set of modulation order parameters is {6}.

[0362] Optionally, the set of modulation order parameters is {4,5,6}.

[0363] Preferably, the modulation order Qm supported in the downlink direction includes at least 2, 4, 6, and 8.

[0364] Preferably, the modulation order Qm supported in the uplink direction includes at least 1, 2, 4, and 6.

[0365] Optionally, the modulation orders supported in the downlink direction include 2, 4, 6, 8, and 10.

[0366] Optionally, the modulation orders supported in the downlink direction include 2, 4, 6, 8, 10, and 11.

[0367] Optionally, the modulation orders supported in the uplink direction include 1, 2, 4, 6, and 8.

[0368] Optionally, the modulation orders supported in the uplink direction include 1, 2, 4, 6, 8, and 10.

[0369] It should be noted that in this application example, 256QAM modulation does not support sub-block interleaving.

[0370] From a technical perspective, extensive research has revealed that the technical solution of this embodiment can achieve different benefits depending on the circumstances. On the one hand, it can obtain SNR performance gains (between 0.1dB and 0.35dB). On the other hand, since adding sub-block interleavers leads to hardware complexity and latency, the scope of application is limited according to the modulation method, thereby greatly reducing the number of interleaving patterns and reducing interleaving complexity.

[0371] Specific Sub-Example 4

[0372] Whether sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information consists of a preset set of parameters for the code rate R, the modulation order Qm (also known as a preset modulation order parameter set), and a preset threshold R for the code rate. th .

[0373] Furthermore, if the code rate R is less than a preset code rate threshold and the modulation order Qm belongs to a preset modulation order parameter set, sub-block interleaving is performed; if the code rate R is greater than the preset code rate threshold or the modulation order Qm does not belong to the preset modulation order parameter set, sub-interleaving is not performed. Here, the code rate is a real number greater than 0 and less than 1. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to, both of which fall within the scope of protection of this application.

[0374] Optionally, the preset bitrate threshold is a real number greater than 0.30 and less than 0.85. Optionally, the preset bitrate threshold is a real number greater than 0.40 and less than 0.75. Optionally, the preset bitrate threshold is a real number greater than 0.45 and less than 0.70. Optionally, the preset bitrate threshold is a real number greater than or equal to 0.50 and less than 0.6. Optionally, the preset bitrate threshold is a real number greater than or equal to 0.50 and less than 0.55. Optionally, the preset bitrate threshold is 1 / 2, 7 / 16, 9 / 16, 5 / 8, or 2 / 3.

[0375] Optionally, the preset code rate threshold is obtained based on the modulation order Qm corresponding to the transport block.

[0376] Optionally, if the first modulation order Qm1 is less than the second modulation order Qm2, the first code rate threshold R corresponding to the first modulation order Qm1 is... th1 The second code rate threshold R is less than the second modulation order Qm2. th2 .

[0377] Optionally, when Qm = 4, the preset threshold R of the bit rate is... th It is a real number greater than or equal to 0.5 and less than or equal to 0.65.

[0378] Optionally, when Qm = 4, the preset threshold R of the bit rate is... th=553 / 1024 or 616 / 1024.

[0379] Optionally, when Qm = 6, the preset threshold R of the bit rate is... th It is a real number that is greater than or equal to 0.55 and less than or equal to 0.675.

[0380] Optionally, when Qm = 6, the preset threshold R of the bit rate is... th = 616 / 1024 or 666 / 1024.

[0381] Optionally, when Qm = 8, the preset threshold R of the bit rate is... th It is a real number greater than or equal to 0.65 and less than or equal to 0.8.

[0382] Optionally, when Qm = 8, the preset threshold R of the bit rate is... th =682.5 / 1024 or 711 / 1024.

[0383] Optionally, when Qm = 10, the preset threshold R of the bit rate is... th = is a real number greater than or equal to 0.75 and less than or equal to 0.85.

[0384] Optionally, when Qm = 10, the preset threshold R of the bit rate is... th =805.5 / 1024.

[0385] It should be noted that one implementation of the bitrate in this application is the target bitrate, and another implementation of the bitrate in this application is the effective bitrate (i.e., the actual bitrate). This concept applies to all content and all embodiments protected in this application.

[0386] From a technical perspective, extensive research has revealed that the technical solution in this embodiment can yield different benefits depending on the circumstances. On one hand, it can achieve SNR performance gains (between 0.1dB and 0.35dB). On the other hand, since adding sub-block interleavers leads to hardware complexity and latency, its application is limited based on the code rate and modulation method, thereby greatly reducing the number of interleaving patterns and interleaving complexity.

[0387] Specific Sub-Example 5

[0388] Whether sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information includes the higher-layer configuration signaling and MCS indexes of the MCS table configured by the base station. Optionally, the predefined condition information may also include a first preset MCS index set and a second preset MCS index set.

[0389] If the MCS index belongs to either the first preset MCS index set or the second preset MCS index table, sub-block interleaving is performed; if the MCS index belongs to neither the first preset MCS index set nor the second preset MCS index table, sub-block interleaving is not performed. The first preset MCS index set belongs to the set [i...]. a i b The second preset MCS index set belongs to the set [i] c i d ], i a i b i c i d All are positive integers, i a b i c d set [i a i b ] indicates greater than or equal to i a and less than or equal to i b The set of all integers, set [i c i d ] indicates greater than or equal to i c and less than or equal to i d The set of all integers with value i a The MCS index indicates the lowest code rate R supported in the MCS table when the modulation order Qm is 4. min The modulation order Qm = 4, and the value is i. c The MCS index indicates the lowest code rate R supported in the MCS table when the modulation order Qm is 6. min The modulation order Qm = 6.

[0390] Furthermore, i b equals i a +3 or i a +4 or i a +5 or i a +6.

[0391] Furthermore, i d equals i c +3 or i c +4 or i c +5 or i c +6 or i c +7.

[0392] ​​From a technical perspective, extensive research has revealed that the technical solution in this embodiment can yield different benefits depending on the circumstances. On one hand, it can achieve SNR performance gains (between 0.1dB and 0.35dB). On the other hand, since adding sub-block interleavers leads to hardware complexity and latency, its application is limited based on the code rate and modulation method, thereby greatly reducing the number of interleaving patterns and interleaving complexity.

[0393] Specific Sub-Example 6

[0394] Whether sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information includes the number of code blocks, C. b Optionally, the predefined condition information also includes the number of code blocks C. b The preset threshold (also known as the preset number of code blocks threshold).

[0395] Furthermore, if the number of code blocks C b If the value is greater than a preset threshold, sub-block interleaving is performed; if the value is less than the preset threshold, sub-block interleaving is not performed. Where C... b It is a positive integer greater than or equal to 1. It should be noted that the above "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0396] From a technical perspective, extensive research has shown that the technical solution in this embodiment can achieve different benefits depending on the situation. When the number of code blocks is large, performing interleaving within the code block set can obtain sufficient frequency diversity gain, improving system performance while almost not increasing processing latency. When the number of code blocks is small, interleaving within the code block set is not performed, otherwise it will cause time delay and will not bring significant diversity gain.

[0397] Specific Sub-Example 7

[0398] Whether the following sub-block interleaving is supported is determined based on predefined condition information, where the predefined condition information is the transport block size. Optionally, the predefined condition information also includes a transport block size threshold.

[0399] Furthermore, if the transport block size is greater than a preset threshold, sub-block interleaving is performed; if the transport block size is smaller than the preset threshold, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0400] From a technical perspective, extensive research has shown that the technical solution in this embodiment can achieve different benefits depending on the situation. When the transport block is large, performing interleaving within the code block set can obtain sufficient frequency diversity gain, improving system performance while almost not increasing processing latency. When the transport block is small, interleaving within the code block set is not performed, otherwise it will cause time delay and will not bring significant diversity gain.

[0401] Specific Sub-Example 8

[0402] Whether the following sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information is higher-layer configuration enabling signaling. Optionally, the predefined condition information also includes predefined interleaving enabling status, which includes either enabling predefined interleaving or disabling predefined interleaving.

[0403] Furthermore, if the higher-layer configuration signaling enables predefined interleaving, sub-block interleaving is performed; if the higher-layer configuration signaling does not enable sub-block interleaving, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0404] Specific Sub-Implementation Example 9

[0405] Whether to support the following sub-block interleaving is determined based on predefined condition information. This predefined condition information is a control information format. Optionally, the predefined condition information may also include enabling or disabling sub-block interleaving.

[0406] Furthermore, if the control information format for scheduling the transport block is a none fallback control information format, sub-block interleaving is performed; if the control information format for scheduling the transport block is a fallback control information format, sub-block interleaving is not performed. It should be noted that the aforementioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0407] Furthermore, if the control information format for scheduling the transport block is the downlink control information format for downlink scheduling indicated by index N2, sub-block interleaving is performed; if the control information format for scheduling the transport block is the downlink control information format for downlink scheduling indicated by index N1, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to. Where N1 and N2 are positive integers greater than or equal to, and N1... <N2。

[0408] Furthermore, if the control information format for scheduling the transport block is the downlink control information format for uplink scheduling indicated by index M2, sub-block interleaving is performed; if the control information format for scheduling the transport block is the downlink control information format for uplink scheduling indicated by index M1, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to. Where M1 and M2 are positive integers greater than or equal to, and M1... <M2。

[0409] It should be noted that the fallback control information format is used to maintain the UE's connection when coverage deteriorates, and its load is relatively small. Interleaving between code blocks offers limited performance gains and introduces complexity, so non-interleaving is preferable. Generally, the fallback control information format has a smaller index, while the none fallback control information format has a larger index.

[0410] It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to. For example, in the 5G NR standard, the fallback control information format is DCI format0_0 or DCI format1_0, and the none fallback control information format is DCI format0_1 or DCI format1_1.

[0411] Specific Sub-Example 10

[0412] Whether the following sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information is the Radio Network Temporary Identifier (RNTI). Furthermore, the RNTI includes either a first-type RNTI or a second-type RNTI.

[0413] Furthermore, if the corresponding RNTI is a Type I RNTI, sub-block interleaving is performed; if the corresponding RNTI is a Type II RNTI, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0414] Furthermore, the first type of RNTI includes at least one of the following: Cell Radio Network Temporary Identifier (C-RNTI), CS-RNTI, and RNTI corresponding to the second channel coding information; the second type of RNTI includes at least one of the following: SI-RNTI, RA-RNTI, P-RNTI, and TC-RNTI. The corresponding RNTI refers to the Radio Network Temporary Identifier (RNTI) scrambled onto the CRC corresponding to the control information scheduling the transport block.

[0415] Specific Sub-Implementation Example 11

[0416] Whether the following sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information is the search space. Furthermore, the search space includes user-owned search space or public search space.

[0417] Furthermore, if the corresponding search space is a user-private search space, sub-block interleaving is performed; if the corresponding search space is a public search space, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0418] Specific Sub-Example 12

[0419] Whether sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information refers to the link direction.

[0420] Furthermore, if the link direction is downlink, sub-block interleaving is performed; if the link direction is uplink, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0421] Furthermore, if the link direction is uplink, sub-block interleaving is performed; if the link direction is downlink, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0422] Specific Sub-Example 13

[0423] Whether the following sub-block interleaving is supported is determined based on predefined condition information. This predefined condition information is the waveform type, which can be either CP-OFDM or DFTS-OFDM.

[0424] Furthermore, if the waveform is a CP-OFDM waveform, sub-block interleaving is performed; if the waveform is a DFTS-OFDM waveform, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0425] Specific Sub-Example 14

[0426] Whether the following sub-block interleaving is supported is determined based on predefined condition information. The predefined condition information is a combination of any two sets of predefined information from sub-examples 1-13.

[0427] Furthermore, if any two sets of predefined condition information in sub-examples 1-10 both support sub-block interleaving, sub-block interleaving is performed; if one of these two sets of predefined condition information does not support sub-block interleaving, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0428] Specific Sub-Example 15

[0429] Whether the following sub-block interleaving is supported is determined based on predefined condition information. The predefined condition information is a combination of any three predefined information items from sub-examples 1-13.

[0430] Furthermore, if any three predefined condition information in sub-examples 1-13 support sub-block interleaving, sub-block interleaving is performed; if any one of these three predefined condition information does not support sub-block interleaving, sub-block interleaving is not performed. It should be noted that the above-mentioned "greater than" and "less than" thresholds can also include two variations: greater than or equal to and less than, and greater than and less than or equal to.

[0431] Step 506 has several parallel implementation methods. The first implementation method is code block concatenation, and the second implementation method is interleaving within the code block set and code block set concatenation.

[0432] First optional implementation method:

[0433] Step S506, code block concatenation: After interleaving the code blocks of each code block, the output codeword bits are concatenated in sequence to obtain a concatenated codeword sequence.

[0434] Second alternative implementation method:

[0435] Step S506, interleaving within the code block set and concatenating the code block sets:

[0436] If one of the following is supported: inter-block interleaving within a block set, inter-block interleaving, or inter-block interleaving, then C bThe interleaved sequence is divided into Mg interleaved sequence sets. Multiple interleaved sequences from each set are interleaved and concatenated to obtain their respective interleaved and concatenated bit sequences. The Mg interleaved and concatenated sequences (or the concatenated and interleaved sequences corresponding to each of the Mg code block sets) are then concatenated sequentially to obtain the concatenated output sequence. This step is omitted if not supported. Here, Mg is a positive integer greater than or equal to 2, and Mg is less than C. b .

[0437] Equivalent to the previous paragraph, if one of the following is supported: interleaving between code blocks within a code block set, interleaving between code blocks, or interleaving within a code block set, then C will... b The code block is divided into Mg code block groups, and the interleaved sequences of multiple code blocks corresponding to each code block group are interleaved and concatenated to obtain the interleaved and concatenated bit sequence for each code block group. The Mg interleaved and concatenated sequences (or the concatenated and interleaved sequences corresponding to each of the Mg code block sets) are concatenated in order to obtain the output sequence after code block concatenation. If not supported, this step is not performed. Where Mg is a positive integer greater than or equal to 2, and Mg is less than C. b .

[0438] It should be noted that, as a technical effect of this application, under the given modulation order Qm and given code rate, the sub-block interleaving pattern equivalently realizes the column permutation of the basic graph matrix of the structured LDPC code, better achieves the optimal matching of the degree distribution of the LDPC code and the reliability of the modulation bits, thereby better achieving the performance optimization of high-order modulation. At the same time, the scheme of this application has the best implementation complexity and system compatibility while being compatible with existing schemes.

[0439] Step S507, Scrambling: The input bit sequence is scrambled to obtain a scrambled sequence. For the scrambling operation, a binary XOR operation (or modulo-2 addition) is performed on the scrambled data bit sequence using a generated pseudo-random sequence. Additionally, if the bit to be scrambled is a placeholder bit, the scrambled bit will be either 1 or the original bit.

[0440] Step S508, Modulation mapping: Modulate the input bit sequence to obtain a modulation symbol sequence, that is, obtain a codeword stream.

[0441] Optionally, the input bit sequence of length Mb is divided into multiple bit groups in order of Qm bits, and each bit group is mapped to a constellation modulation symbol in turn to obtain a complex modulation symbol sequence of length Ms, where Qm is the modulation order.

[0442] Optionally, the modulation scheme includes one of the following: Pi / 2BPSK, QPSK, 16QAM, 64QAM, 256QAM, and 1024QAM. The modulation order represents the number of bits carried by each constellation modulation symbol, and the corresponding modulation order is 1, 2, 4, 6, 8, or 10.

[0443] Optionally, for each Qm bit of the modulation map, the preceding bits have high reliability and the following bits have low reliability, where Qm is 4, 6, 8 or 10.

[0444] Optionally, the modulation method is probabilistic shaping modulation, geometric shaping modulation, or AI-generated modulation.

[0445] Step S509, Layer Mapping: The modulation symbol sequence of the codeword stream will be mapped to the transport layer N. L There are N transport layers, where N L Greater than or equal to 1.

[0446] Optionally, following the input modulation symbol sequence from front to back, at every N... L Each group of modulation symbols is mapped to a layer in a cyclical manner, according to the layer index in ascending order. Where N... L It refers to the number of transmission layers.

[0447] Step S510, Antenna Port Mapping: Map each layer modulation symbol sequence after layer mapping to one or more antenna ports.

[0448] Furthermore, when the link direction is uplink, this process is also called MIMO precoding, which is implemented using a precoding matrix W. The precoding matrix is ​​determined by two different methods: codebook-based and non-codebook-based. In the codebook-based method, the matrix is ​​determined by information specified in the DCI and some additional configurations in the RRC message. In the non-codebook-based method, the precoding matrix is ​​determined by the measurement results of the measurement reference signal.

[0449] Furthermore, when the link direction is downlink, there is no precoding matrix, or the precoding matrix is ​​considered to be an identity matrix, directly mapping each layer of symbol sequence to one or more antenna ports.

[0450] Step S511, Resource Mapping: Map the data symbol sequence of each antenna port to a resource element.

[0451] Optionally, the resource unit is a resource block.

[0452] Optionally, the resource unit is a time-frequency resource element.

[0453] Optionally, the resource unit is a time unit OFDM symbol.

[0454] Step S512, generate waveform: perform OFDM waveform generation on the symbol sequence on the resource unit to obtain the time-domain OFDM waveform.

[0455] It should be noted that the OFDM waveform generation mentioned above refers to the inverse Fourier transform (IFFT) and the addition of CP.

[0456] The OFDM waveform symbol sequence of the baseband is then converted from digital to analog and transmitted through intermediate frequency circuits and radio frequency circuits.

[0457] It should be noted that between steps S509 and S510, if the link direction is uplink and the base station configuration signaling enables transform precoding (i.e., the uplink waveform is DFTS-OFDM waveform), then transform precoding operation exists; otherwise, this transform precoding operation does not exist.

[0458] Preferred embodiment 2

[0459] According to one aspect of this optional embodiment, the signal processing method provided by this optional embodiment can be applied to the transmitting communication equipment of next-generation 6G communication systems and subsequent communication systems (6G and beyond), such as base station or terminal or relay station or satellite communication equipment, or the transmitting communication equipment of next-generation fixed access wireless communication systems, such as AP or terminal.

[0460] like Figure 5 As shown, Figure 5 A signal processing method according to a preferred embodiment of this application is provided, which is applied to the transmitting end. Figure 5 The device executing the given signal processing method is a transmitter. The signal processing method includes at least one of the following steps:

[0461] Step S501, CRC addition to transport block: Calculate the CRC check bit sequence based on the given CRC (Cyclic Redundancy Check) polynomial and the input transport block sequence, and add the generated CRC check bit sequence to the end of the transport block to obtain the transport block after addition.

[0462] Step S502, code block segmentation and code block CRC addition; determine the number of code blocks C b If the number of code blocks C b If the value is greater than 1, the input data sequence is segmented into code blocks, and a CRC is added to the segmented code blocks or code block groups to obtain the code block bit sequence.

[0463] Furthermore, the number of code blocks C b It is based on B tb and K cb The obtained, of which B tb It is the total length of the transport block and the transport block CRC, K cb The code block size for encoding the largest input channel.

[0464] Optionally, C b =ceil(B tb / (K cb -L cb Among them, L cb It is the length of the CRC block.

[0465] Furthermore, the code block size K of the input channel coding in It is based on B tb and K cb Obtained.

[0466] Optionally, the code block size K of the input channel coding in =B tb ' / C b Where, if B≤K cb Then B tb =B; otherwise, B tb ′=B tb +C b *L cb .

[0467] Optionally, a block CRC can be added to each segmented block.

[0468] Optionally, the number of code blocks after segmentation is C. b One, will C b Each segment of the code block is divided into Mc groups, and a code block group CRC is added to each group. The code block group CRC is generated based on the data of the group and a CRC generator polynomial encoding, where Mc is a positive integer greater than or equal to 1.

[0469] There is an alternative to the above S502 step, which only involves code block segmentation and does not involve adding code block CRC.

[0470] Step S503, Channel coding: For C b Each code block sequence in the input code block bit sequence is individually channel-coded to generate C. b A number of lengths N r The mother codeword.

[0471] Furthermore, the information bit sequence encoded by the input channel is After channel coding, the resulting mother codeword sequence is:

[0472] Furthermore, the channel coding is either LDPC code or Polar code.

[0473] Furthermore, r is the code block index, r = 0, ..., C b -1.

[0474] Step S504, Bit selection: for C b A number of lengths N r The length of each channel encoded in the mother codeword is N. r The mother codeword is individually bit-selected to obtain C. b A length of E r The sequence after bit selection is used as the bit selection sequence.

[0475] Furthermore, r is the code block index, r = 0, ..., C b -1.

[0476] Specifically, each channel is first encoded to a length of N. r The mother codewords are written separately, each with a length of N. cb In the circular buffer, E is then selected individually from each circular buffer based on the redundant version currently being transmitted. r 1 codeword bit, generate C b The sequence after selecting 1 bit. Where E r It is a positive integer greater than 1, E r This refers to the length of the rate-matched output sequence of the r-th code block, where r is the code block index, r = 0, 1, ..., C. b -1.

[0477] Optionally, if circular cache rate matching is not supported, N cb =N r Otherwise, N cb =min(N) r N ref ), N ref It is a code length that matches the finite cache rate.

[0478] Optionally, N ref It is determined by the number of code blocks C b The code rate R of a finite circular buffer LBRM The maximum number of antenna layers, maximum code rate, maximum modulation order, maximum number of PRBs, and maximum code rate are determined.

[0479] Furthermore, based on predefined condition information, it is determined whether bit selection needs to support sub-block interleaving. If bit selection supports sub-block interleaving, bit selection based on bit interleaving is performed on the mother codeword to obtain a bit selection sequence; if bit selection does not support sub-block interleaving, bit selection is performed on the mother codeword to obtain a bit selection sequence.

[0480] It should be noted that if sub-block interleaving is not supported, the usual bit selection process can be used.

[0481] Furthermore, the bit selection based on bit interleaving of the mother codeword, in one example, includes the following steps:

[0482] Step a1: Determine the final length E of each code block after bit selection. r and the intermediate length (Also known as the intermediate length).

[0483] Furthermore, E r It is based on G, Qm, N L The calculation is as follows, where G is the total number of coded bits used to transmit the transport block, Qm is the modulation order, and N is the total number of coded bits. L It refers to the number of transmission layers.

[0484] Furthermore, in the C b Among the codewords, there is mod(G / (N) L *Qm),C b The sequence length is N after selecting ) bits. L *Qm*ceil(G / (N L *Qm*C b The code block of )) and C b -mod(G / (N L *Qm),C b The sequence length is N after selecting ) bits. L *Qm*floor(G / (N L *Qm*C b )) code blocks.

[0485] Furthermore, E r It is based on the number of resources N occupied by the transport block. RE Qm, N L Calculated.

[0486] Furthermore, E r It is based on the resource allocation information, Qm, N allocated to the transport block. L Calculated.

[0487] further, It is based on Er and the increase value Z c Calculated. Optionally,

[0488] further, It is based on G, Qm, N L and Z c The calculation is as follows, where G is the total number of coded bits used to transmit the transport block, Qm is the modulation order, and N is the total number of coded bits. L It is the number of transport layers and Z c It is an increase in value.

[0489] Furthermore, in the C b Among the codewords, there is mod(G / (N) L *Qm),C b The sequence length after selecting ) bits is Z. c *ceil(N L *Qm*ceil(G / (N L *Qm*C b )) / Z c The code block of ) and C b -mod(G / (N L *Qm),C b The sequence length after selecting ) bits is Z. c *floor(N L *Qm*floor(G / (N L *Qm*C b )) / Z c ) code blocks.

[0490] Step a2, from size N cb Select in the circular cache Each codeword bit.

[0491] From the r-th parent codeword, i.e., the bit sequence Perform bit selection to obtain the r-th bit sequence after bit selection. In one example, the bit selection sequence of the r-th code block is determined based on the redundancy version, and the redundancy version number of the currently transmitted code block is denoted as rv. id ,rv id It can be equal to 0, 1, 2, or 3, r = 0, 1, ..., C b -1. e r The generation process is shown in the following pseudocode:

[0492]

[0493] Step a3: Perform sub-block interleaving on the input bit sequence, where the size of each sub-block is the boost value Z. c .

[0494] Furthermore, the aforementioned sub-block interweaving is first based on the intermediate length. The number of sub-blocks N is determined by the lift value Zc. sub Secondly, the input bit sequence is divided into sub-blocks based on the boost value Zc to obtain N. sub N sub-blocks; then, according to a predefined sub-block interleaving pattern, the N... sub Sub-blocks are interleaved.

[0495] Furthermore, the aforementioned sub-block interweaving is first based on the intermediate length. The number of sub-blocks is determined by the lift value Zc. Next, the input bit sequence is divided into sub-blocks in order of the boost value Zc, resulting in N. sub N sub-blocks, each of which has a length of Zc; then the N sub-blocks are interleaved according to a predefined sub-block pattern. sub Each sub-block undergoes sub-block interleaving; finally, the N-level cascaded interleaving is completed. sub Individual blocks.

[0496] Furthermore, the sub-block interleaving pattern is from 0 to N. sub -1 of N sub A sequence of integers arranged in a predefined interleaving order.

[0497] Furthermore, the aforementioned sub-block interleaving refers to performing sub-block interleaving on all sub-blocks according to a predefined sub-block interleaving pattern.

[0498] Furthermore, after concatenating and interleaving all sub-blocks, the resulting output code block interleaved bit sequence is obtained.

[0499] Furthermore, the description of determining whether sub-block interleaving is supported based on predefined condition information includes the relevant descriptions of all specific technical features in preferred embodiment 1. Even further, it includes specific sub-embodiments 1 to 15, which are completely identical. These will not be repeated here.

[0500] Furthermore, a bit interleaving index is obtained according to the sub-block interleaving method described above; then, interleaving from the input bit sequence to the output bit sequence is implemented based on the bit interleaving index. The interleaving index is used to determine the input interleaved bit position corresponding to the interleaved bit position of each output, or the output interleaved bit position corresponding to the interleaved bit position of each input.

[0501] Furthermore, the sub-block interleaving is implemented according to the following pseudocode: Let the codeword bits of the input sub-block interleaving be x0, x1, ..., x N-1 The codeword bits for the output sub-block interleaving are y0, y1, ..., y N-1 Where N is the interlacing length.

[0502]

[0503] Optionally,

[0504] Step a4, from length of Sequence selection E after sub-block interleaving r Each codeword bit is used as the final output sequence for bit selection.

[0505] Furthermore, from the length of Select the first E from the sequence after the sub-blocks are interleaved r Each codeword bit is used as the final output sequence for bit selection.

[0506] Furthermore, this preferred embodiment also includes all the sub-block interleaving execution methods in preferred embodiment one. That is to say, all the sub-block interleaving execution schemes in embodiment one are also applicable to this preferred embodiment, and these sub-block interleaving execution methods are all within the protection scope of this preferred embodiment.

[0507] Furthermore, this preferred embodiment also includes a method for determining whether sub-block interleaving is supported, which also includes all 15 specific sub-embodiments in preferred embodiment one, and these embodiments are all within the protection scope of this preferred embodiment.

[0508] Furthermore, this preferred embodiment also includes the method for determining all sub-block interlacing patterns in preferred embodiment one. That is, the method for determining all sub-block interlacing patterns in embodiment one is also applicable to this preferred embodiment, and these methods for determining sub-block interlacing patterns all fall within the protection scope of this preferred embodiment.

[0509] It should be noted that extensive simulations show that preferred embodiment 2 has slightly better link performance than preferred embodiment 1.

[0510] Step S505, Code Block Interleaving: Interleave the input sequence of each code block to obtain C b The interleaved sequence of outputs.

[0511] Furthermore, the input bit sequence of each code block Individually interleaved into an output bit sequence

[0512] Furthermore, based on the modulation order Q m The input bit sequence of each code block Individually interleaved into an output bit sequence

[0513] Furthermore, the input bit sequence can be interleaved into an output bit sequence using the following method:

[0514]

[0515] Furthermore, based on the modulation order Q m Number of transport layers N L The input bit sequence of each code block Individually interleaved into an output bit sequence

[0516] Furthermore, based on the modulation order Q m Number of transport layers N L The layer indication information will be the bit sequence of the input for each code block. Individually interleaved into an output bit sequence

[0517] Furthermore, a bit interleaving index is obtained according to the interleaving method described above; then, interleaving from the input bit sequence to the output bit sequence is performed based on the bit interleaving index. The interleaving index is used to determine the input interleaved bit position corresponding to the interleaved bit position of each output, or the output interleaved bit position corresponding to the interleaved bit position of each input.

[0518] Step 506 has several parallel implementation methods. The first implementation method is code block concatenation, and the second implementation method is interleaving within the code block set and code block set concatenation.

[0519] First optional implementation method:

[0520] Step S506, code block concatenation: After interleaving the code blocks of each code block, the output codeword bits are concatenated in sequence to obtain a concatenated codeword sequence.

[0521] Second alternative implementation method:

[0522] Step S506, interleaving within the code block set and concatenating the code block sets:

[0523] If one of the following is supported: inter-block interleaving within a block set, inter-block interleaving, or inter-block interleaving, then C b The interleaved sequence is divided into Mg interleaved sequence sets. Multiple interleaved sequences from each set are interleaved and concatenated to obtain their respective interleaved and concatenated bit sequences. The Mg interleaved and concatenated sequences (or the concatenated and interleaved sequences corresponding to each of the Mg code block sets) are then concatenated sequentially to obtain the concatenated output sequence. This step is omitted if not supported. Here, Mg is a positive integer greater than or equal to 2, and Mg is less than C. b .

[0524] Equivalent to the previous paragraph, if one of the following is supported: interleaving between code blocks within a code block set, interleaving between code blocks, or interleaving within a code block set, then C will...b The code block is divided into Mg code block groups, and the interleaved sequences of multiple code blocks corresponding to each code block group are interleaved and concatenated to obtain the interleaved and concatenated bit sequence for each code block group. The Mg interleaved and concatenated sequences (or the concatenated and interleaved sequences corresponding to each of the Mg code block sets) are concatenated in order to obtain the output sequence after code block concatenation. If not supported, this step is not performed. Where Mg is a positive integer greater than or equal to 2, and Mg is less than C. b .

[0525] It should be noted that, as a technical effect of this application, under the given modulation order Qm and given code rate, the sub-block interleaving pattern equivalently realizes the column permutation of the basic graph matrix of the structured LDPC code, better achieves the optimal matching of the degree distribution of the LDPC code and the reliability of the modulation bits, thereby better achieving the performance optimization of high-order modulation. At the same time, the scheme of this application has the best implementation complexity and system compatibility while being compatible with existing schemes.

[0526] Step S507, Scrambling: The input bit sequence is scrambled to obtain a scrambled sequence. For the scrambling operation, a binary XOR operation (or modulo-2 addition) is performed on the scrambled data bit sequence using a generated pseudo-random sequence. Additionally, if the bit to be scrambled is a placeholder bit, the scrambled bit will be either 1 or the original bit.

[0527] Step S508, Modulation mapping: Modulate the input bit sequence to obtain a modulation symbol sequence, that is, obtain a codeword stream.

[0528] Optionally, the input bit sequence of length Mb is divided into multiple bit groups in order of Qm bits, and each bit group is mapped to a constellation modulation symbol in turn to obtain a complex modulation symbol sequence of length Ms, where Qm is the modulation order.

[0529] Optionally, the modulation scheme includes one of the following: Pi / 2BPSK, QPSK, 16QAM, 64QAM, 256QAM, and 1024QAM. The modulation order represents the number of bits carried by each constellation modulation symbol, and the corresponding modulation order is 1, 2, 4, 6, 8, or 10.

[0530] Optionally, for each Qm bit of the modulation map, the preceding bits have high reliability and the following bits have low reliability, where Qm is 4, 6, 8 or 10.

[0531] Optionally, the modulation method is probabilistic shaping modulation, geometric shaping modulation, or AI-generated modulation.

[0532] Step S509, Layer Mapping: The modulation symbol sequence of the codeword stream will be mapped to one or more layers in the transport layer.

[0533] Optionally, following the input modulation symbol sequence from front to back, each group of modulation symbols is mapped to each layer in a round-robin fashion, according to the layer index in ascending order, where L is the number of transmission layers.

[0534] Step S510, Antenna Port Mapping: Map each layer modulation symbol sequence after layer mapping to one or more antenna ports.

[0535] Furthermore, when the link direction is uplink, this process is also called MIMO precoding, which is implemented using a precoding matrix W. The precoding matrix is ​​determined by two different methods: codebook-based and non-codebook-based. In the codebook-based method, the matrix is ​​determined by information specified in the DCI and some additional configurations in the RRC message. In the non-codebook-based method, the precoding matrix is ​​determined by the measurement results of the measurement reference signal.

[0536] Furthermore, when the link direction is downlink, there is no precoding matrix, or the precoding matrix is ​​considered to be an identity matrix, directly mapping each layer of symbol sequence to one or more antenna ports.

[0537] Step S511, Resource Mapping: Map the data symbol sequence of each antenna port to a resource element.

[0538] Optionally, the resource unit is a resource block.

[0539] Optionally, the resource unit is a time-frequency resource element.

[0540] Optionally, the resource unit is a time unit OFDM symbol.

[0541] Step S512, waveform generation: Perform OFDM waveform generation on the symbol sequence on the resource unit to obtain a time-domain OFDM waveform. It should be noted that the OFDM waveform generation refers to the Inverse Fourier Transform (IFFT) and CP addition processing.

[0542] The OFDM waveform symbol sequence of the baseband is then converted from digital to analog and transmitted through intermediate frequency circuits and radio frequency circuits.

[0543] It should be noted that between steps S510 and S511, if the link direction is uplink and the base station configuration signaling enables transform precoding (i.e., the uplink waveform is DFTS-OFDM waveform), then transform precoding operation exists; otherwise, this transform precoding operation does not exist.

[0544] The signal processing method provided in this application embodiment has been described in detail from the perspective of the transmitting end. The signal deprocessing method provided in this application embodiment will be described from the perspective of the receiving end.

[0545] In one embodiment, Figure 7 This is a flowchart of a signal deprocessing method provided in an embodiment of this application. This embodiment is applied to the case of optimizing the link performance of LDPC codes. This embodiment can be executed by a receiving end. For example, the receiving end can be a terminal device or a base station. Figure 7 As shown, this embodiment includes: S710-S750.

[0546] S710. Perform decoder block interleaving on the soft bit sequence of the code block to obtain the deinterleaved soft codeword sequence.

[0547] S720. Perform de-bit selection on the deinterleaved soft codeword sequence to obtain the mother codeword.

[0548] S730: Perform LDPC decoding on the mother codeword to obtain the decoded code block.

[0549] S740. Perform decoding block segmentation and decoding block verification on the decoded code block to obtain the added transmission block.

[0550] S750. De-verify the added transport block to obtain the transport block; wherein, determine whether the decoding block interleaving supports sub-block deinterleaving based on predefined condition information.

[0551] In one embodiment, Figure 8 This is a flowchart of another signal deprocessing method provided in an embodiment of this application. This embodiment is applied to the case of optimizing the link performance of LDPC codes. This embodiment can be executed by the receiving end. Figure 8 As shown, this embodiment includes: S810-S850.

[0552] S810. Perform decoder block interleaving on the soft bit sequence of the code block to obtain the deinterleaved soft codeword sequence.

[0553] S820. Perform de-bit selection on the deinterleaved soft codeword sequence to obtain the mother codeword.

[0554] S830: Perform LDPC decoding on the mother codeword to obtain the decoded code block.

[0555] S840: Perform decoding block segmentation and decoding block verification on the decoded code block to obtain the added transmission block.

[0556] S850. De-verify the added transport block to obtain the transport block; wherein, determine whether the de-bit selection supports sub-block deinterleaving based on predefined condition information.

[0557] In one embodiment, Figure 9 This is a schematic diagram of another signal deprocessing method provided in the embodiments of this application. Figure 9 The method shown is executed by a receiving end, and the method includes:

[0558] Step S901, Waveform Detection: Detecting the received waveform signal, which is the reverse process of step S512. This step also includes step S512, which relates to all technical features and / or sub-implementations.

[0559] Step S902, Physical resource demapping: the reverse process of step 511 physical resource mapping. This step also includes step S511 involving all technical features and / or sub-implementations.

[0560] Step S903, Antenna Port Demapping: The reverse process of step 510, antenna port mapping. This step also includes step S510 involving all technical features and / or sub-implementations.

[0561] Step S904, De-mapping: The reverse process of step 509, layer mapping. This step also includes step S509, which involves all technical features and / or sub-implementations.

[0562] Step S905, Demodulation: Demapping the constellation points on the constellation diagram is the reverse process of modulation mapping in step 508. This step also includes step S508, which involves all technical features and / or sub-implementations.

[0563] Step S906, Descrambling: The reverse process of step 507 scrambling. This step also includes step S507 which relates to all technical features and / or sub-implementations.

[0564] Step S907 has two parallel solutions, including the following:

[0565] One of the parallel schemes in step S907 is code block deconcatenation: the input concatenated code block sequence is deconcatenated (code block segmentation) to obtain C. b The soft bit sequence of each code block. This is the reverse process of code block concatenation in step 506. This step also includes step S506 involving all technical features and / or sub-implementations.

[0566] The code block set deconcatenation and code block set internal deinterleaving of the second parallel scheme in step S907 are the reverse process of code block set internal interleaving and code block set concatenation in step 507.

[0567] Step S908, code block deinterleaving: for C b The soft bit sequences of each code block are deinterleaved to obtain C. b The codeword sequence output after deinterleaving. This is the deinterleaving process of step 505. This step also includes step S205 involving all technical features and / or sub-implementations. Code block deinterleaving includes two sub-steps: the first sub-step deinterleaving based on the deinterleaved bits according to the modulation order, and the second sub-step including sub-block deinterleaving based on the boost value.

[0568] Step S909, De-rate matching (de-bit selection): The reverse process of step 504, rate matching (bit selection). This step also includes step S504, which relates to all technical features and / or sub-implementations.

[0569] Step S910, Channel decoding: For C b Each code block sequence in the input mother codeword sequence is individually LDPC decoded or Polar decoded to generate C. b A decoded code block of length N. This is the reverse process of channel coding in step 503. This step also includes step S503 involving all technical features and / or sub-implementations.

[0570] Step S911, Decoding Block Segmentation and Decoding Block CRC: Based on the given CRC (Cyclic Redundancy Check) polynomial and input sequence, perform CRC verification of the transmission block to determine whether the transmission block has been correctly received. This step also includes step S502, which involves all technical features and / or sub-implementations.

[0571] Step S912, Decode the transport block CRC: Based on the given CRC (Cyclic Redundancy Check) polynomial and input sequence, perform a CRC check on the transport block to determine whether the transport block has been correctly received. This step also includes step S501, which relates to all technical features and / or sub-implementations.

[0572] It should be noted that between steps S903 and S904, if the link direction is uplink and the base station configuration signaling enables detransform precoding (i.e., the uplink waveform is DFTS-OFDM waveform), then a detransform precoding operation exists; otherwise, this detransform precoding operation does not exist.

[0573] The foregoing has detailed examples of signal processing and signal deprocessing methods provided in the embodiments of this application. It is understood that, in order to implement the above functions, the transmitting and receiving ends include corresponding hardware structures and / or software modules for performing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0574] In one embodiment, Figure 10 This is a schematic diagram of a signal processing apparatus provided in an embodiment of this application. The apparatus 1000 includes a processing unit 1010. The processing unit 1010 can be used to perform the actions described in the embodiments of the above-described signal processing method, wherein the above-described signal processing method includes all previously protected data features.

[0575] The processing unit is configured to add a CRC bit sequence to the transport block to obtain the transport block after the addition.

[0576] The added transport block is sequentially segmented into code blocks and CRC bit sequences are added to obtain the code block bit sequence.

[0577] Each code block bit sequence is LDPC encoded to obtain the mother codeword;

[0578] Bit selection is performed on each mother codeword to obtain the bit selection sequence;

[0579] Each bit selection sequence is subjected to code block interleaving to obtain a code block interleaving sequence; wherein, the code block interleaving is determined to support sub-block interleaving based on predefined condition information.

[0580] In one embodiment, each bit selection sequence is subjected to code block interleaving to obtain a code block interleaved sequence, including:

[0581] If code block interleaving supports sub-block interleaving, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain the sub-block interleaved sequence, and the sub-block interleaved sequence is bit interleaved based on the modulation order to obtain the code block interleaved sequence.

[0582] If the code block interleaving does not support sub-block interleaving, bit interleaving is performed on the bit selection sequence based on the modulation order to obtain the code block interleaved sequence.

[0583] In one embodiment, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, including:

[0584] The number of sub-blocks is determined based on the sequence length of the bit selection sequence and the boost value;

[0585] The bit selection sequence is interleaved with sub-blocks according to the number of sub-blocks to obtain the sub-block interleaved sequence.

[0586] In one embodiment, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, including:

[0587] The number of sub-blocks is determined based on the sequence length of the bit selection sequence and the boost value;

[0588] The bit selection sequence is divided into sub-blocks based on the boost value, resulting in multiple sub-blocks;

[0589] Multiple sub-blocks are interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence.

[0590] In one embodiment, the bit selection sequence is divided into sub-blocks based on the boost value to obtain multiple sub-blocks, including:

[0591] The bit selection sequence is divided into sub-blocks in order of the boost value Zc as the sub-block size, resulting in N. sub N sub-blocks; of which N sub Each sub-block contains N sub-blocks with a length equal to the promotion value Zc. sub -1 code blocks, and the last code block whose sub-block length is less than or equal to the boost value Zc.

[0592] In one embodiment, the sub-block interleaving pattern is a sequence arranged according to a predefined interleaving order, and the number of values ​​of the sub-block interleaving pattern is equal to the number of sub-blocks obtained by sub-block division, or the number of values ​​of the sub-block interleaving pattern is greater than the number of sub-blocks obtained by sub-block division.

[0593] In one embodiment, the sub-block interleaving pattern is composed of 0, 1, 2, ..., N sub -1 is composed of, and N sub The integers are a sequence arranged in a predefined interleaving order.

[0594] In one embodiment, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, including:

[0595] The sequence length E is selected based on the bit selection sequence. r The number of sub-blocks N is determined by the lift value Zc. sub Where r is the code block index;

[0596] The bit selection sequence is divided into sub-blocks based on the lift value Zc to obtain N. sub Each block;

[0597] If the length of the last sub-block is equal to the lift value Zc, then N is processed according to the predefined sub-block interleaving pattern. sub Each sub-block is interleaved to obtain a sub-block interleaved sequence;

[0598] If the length of the last sub-block is less than the lift value Zc, then apply the predefined sub-block interleaving pattern to N excluding the last sub-block. sub -1 sub-blocks are interleaved, and the position of the last sub-block remains unchanged, resulting in a sub-block interleaving sequence.

[0599] In one embodiment, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, including:

[0600] The sequence length E is selected based on the bit selection sequence. r The number of sub-blocks N is determined by the lift value Zc. sub ;

[0601] The bit selection sequence is divided into sub-blocks based on the lift value Zc to obtain N. sub Each block;

[0602] According to the predefined sub-block interleaving pattern, N is processed... sub Each sub-block is interleaved to obtain a sub-block interleaving sequence; where the sub-block interleaving pattern consists of 0, 1, 2, ..., N. sub -1 is composed of, and N sub The integers are arranged in a predefined interleaving order, and the last number in the sub-block interleaving pattern is N. sub -1.

[0603] In one embodiment, between sub-block partitioning and sub-block interleaving, if the length of the last sub-block among all sub-blocks after sub-block partitioning is less than the boost value, the last sub-block is bit-padded so that the length of the last sub-block is equal to the boost value.

[0604] In one embodiment, before sub-block partitioning, if the rate-matched length of each code block is not an integer multiple of the boost value, bit padding is performed on the rate-matched sequence of each code block, adding Zc*ceil(E) r / Zc)-E r Fill in bits such that the bit-filled sequence is an integer multiple of the boost value.

[0605] In one embodiment, bit stuffing of the last sub-block includes one of the following:

[0606] Fill the last sub-block with Zc*ceil(E) r / Zc)-E r There are placeholders, where ceil indicates rounding up;

[0607] Fill the last sub-block with Zc*ceil(E) r / Zc)-E r One empty bit symbol.

[0608] In one embodiment, multiple sub-blocks are interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence, including:

[0609] Sub-blocks of size 'lift' are interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence.

[0610] In one embodiment, after performing sub-block interleaving on multiple sub-blocks according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence, the method further includes:

[0611] Remove padding bits contained in the sub-block interleaving sequence.

[0612] In one embodiment, each bit selection sequence is subjected to code block interleaving to obtain a code block interleaved sequence, including:

[0613] If the code block interleaving supports sub-block interleaving, the input index sequence of the corresponding bit selection sequence is interleaved based on the number of sub-blocks to obtain the first interleaving index, and bit interleaving is performed on the first interleaving index based on the modulation order to obtain the second interleaving index. The bit selection sequence is then mapped bit by bit according to the second interleaving index.

[0614] If the code block interleaving does not support sub-block interleaving, bit interleaving is performed on the input index sequence of the corresponding bit selection sequence based on the modulation order to obtain the third interleaving index, and bit-by-bit interleaving mapping is performed on the bit selection sequence according to the third interleaving index.

[0615] In one embodiment, each bit selection sequence is subjected to code block interleaving to obtain a code block interleaved sequence, including:

[0616] If the code block interleaving supports sub-block interleaving, the bit selection sequence is interleaved according to the second interleaving index to obtain the code block interleaving sequence; wherein, the second interleaving index is determined according to the sub-block interleaving based on the first interleaving index, the boost value and the sub-block interleaving pattern, the first interleaving index is determined according to the bit interleaving based on the modulation order, and the second interleaving index is a first function of the output index of the code block interleaving sequence;

[0617] If the code block interleaving does not support sub-block interleaving, the bit selection sequence is interleaved according to the third interleaving index to obtain the code block interleaved sequence; wherein, the third interleaving index is determined based on the bit interleaving of the modulation order, and the third interleaving index is the second function of the output index of the code block interleaved sequence.

[0618] In one embodiment, before determining the first interleaving index based on the modulation order bit interleaving, the method further includes:

[0619] The bit selection sequence is padded with bits so that the length of each sub-block is equal to the boost value.

[0620] In one embodiment, after performing code block interleaving on the bit selection sequence according to the second interleaving index to obtain the bit interleaved sequence, the method further includes:

[0621] Remove padding bits contained in the sub-block interleaving sequence.

[0622] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0623] It is obtained from the modulation order and the number of sub-blocks corresponding to the transmission block;

[0624] It is obtained from the modulation order, number of sub-blocks and basic graph index corresponding to the transport block.

[0625] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0626] It is determined based on the MCS index of the modulation and coding scheme corresponding to the transport block;

[0627] It is determined based on the MCS index set corresponding to the transport block, wherein the MCS index set includes at least two adjacent MCS indices in an MCS table;

[0628] It is determined based on the MCS index, the MCS index set, and the modulation order corresponding to the transport block;

[0629] It is determined based on the MCS index and transport layer number corresponding to the transport block;

[0630] It is determined based on the MCS index corresponding to the transport block, the transport layer number, and the number of resource elements in each transport block.

[0631] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0632] It is determined based on the coding rate, coding rate range, and modulation order of the transport block;

[0633] It is determined based on the current transmission redundancy version corresponding to the transmission block;

[0634] It is determined based on the current transmission redundancy version corresponding to the transport block, the system bit puncturing situation, the modulation order, and the coding rate.

[0635] In one embodiment, the predefined condition information includes at least one of the following: modulation order, sequence length of bit selection sequence and boost value; code rate and preset code rate threshold; code rate, preset code rate threshold and modulation order; modulation order and preset set of modulation order parameters for supporting sub-block interleaving; preset set of parameters for code rate and modulation order and preset code rate threshold.

[0636] In one embodiment, the predefined condition information includes at least one of the following: higher-level configuration signaling and MCS index of the MCS table; higher-level configuration signaling, MCS index, first preset MCS index set and second preset MCS index set of the MCS table; number of code blocks; number of code blocks and preset code block number threshold; transport block size; transport block size and preset transport block size threshold.

[0637] In one embodiment, the predefined condition information includes at least one of the following: higher-layer configuration enable signaling; higher-layer configuration enable signaling and predefined interleaving enable conditions; control information format; control information format and sub-block interleaving enable conditions; wireless network temporary identifier; search space.

[0638] In one embodiment, the signal processing apparatus further includes:

[0639] The processing unit 1010 is also configured to concatenate the code block interleaving sequence to obtain the concatenated codeword sequence.

[0640] In one embodiment, code block concatenation is performed on the code block interleaving sequence to obtain a concatenated codeword sequence, including one of the following:

[0641] The code block interleaving sequence is concatenated in order to obtain the concatenated codeword sequence;

[0642] The code block interleaving sequence is divided into multiple sets of code block interleaving sequences. Each code block interleaving sequence is interleaved and concatenated to obtain the corresponding interleaved and concatenated bit sequences. The interleaved and concatenated bit sequences are then concatenated in sequence to obtain the concatenated codeword sequence.

[0643] In one embodiment, the signal processing apparatus further includes:

[0644] The processing unit 1010 is also configured to scramble the control and multiplexed codeword sequence to obtain a scrambled sequence.

[0645] The modulation order of the scrambled sequence is Q. m The modulation mapping yields a sequence of modulation symbols for a codeword stream;

[0646] Map the modulation symbol sequence of the codeword stream to N L There are N transport layers. L Greater than or equal to 1;

[0647] If transform precoding is enabled, for N L The layer modulated symbol sequence is transformed and precoded to obtain N. L Layered complex number symbol sequence;

[0648] Map the complex symbol sequence of each transmission layer to one or more antenna ports;

[0649] Map the complex symbol sequence of each antenna port to a resource element;

[0650] OFDM waveform generation is performed on the complex symbol sequence on the resource unit to obtain the time-domain OFDM waveform.

[0651] The signal processing device provided in this embodiment is configured to achieve... Figure 3 The signal processing method applied to the transmitting end in the illustrated embodiment is similar in principle and technical effect to the signal processing device provided in this embodiment, and will not be described again here.

[0652] In one embodiment, the processing unit 1010 is further configured to add a CRC bit sequence to the transport block to obtain the transport block with the added bits.

[0653] The added transport block is sequentially segmented into code blocks and CRC bit sequences are added to obtain the code block bit sequence.

[0654] Each code block bit sequence is LDPC encoded to obtain the mother codeword;

[0655] Bit selection is performed on each mother codeword to obtain the bit selection sequence;

[0656] Each bit selection sequence is interleaved with code blocks to obtain an interleaved code block sequence; wherein, based on predefined condition information, it is determined whether the bit selection supports sub-block interleaving.

[0657] In one embodiment, bit selection is performed on each mother codeword to obtain a bit selection sequence, including:

[0658] If bit selection supports sub-block interleaving, bit selection based on bit interleaving is performed on the mother codeword to obtain the bit selection sequence;

[0659] If bit selection does not support sub-block interleaving, bit selection is performed on the mother codeword to obtain the bit selection sequence.

[0660] In one embodiment, bit selection based on bit interleaving is performed on the mother codeword to obtain a bit selection sequence, including:

[0661] Determine the final length E of the bit selection for each code block. r and middle length

[0662] Select from the master codeword One codeword bit;

[0663] right Each codeword bit is interleaved into a sub-block to obtain a sub-block interleaved sequence;

[0664] From length Select E from the sub-block interleaving sequence r Each codeword bit is used as a bit selection sequence.

[0665] In one embodiment, the bit selection final length E r Based on the total number of coded bits G, modulation order Qm, and transmission layer N of the transport block L It has been confirmed.

[0666] In one embodiment, the intermediate length The final length and boost value Z are selected based on the bits. c It has been confirmed.

[0667] In one embodiment, the intermediate length

[0668] In one embodiment, for Each codeword bit is interleaved into sub-blocks to obtain an interleaved sub-block sequence, including:

[0669] Based on the middle length and the increase value Z c Determine the number of sub-blocks N sub ;

[0670] Based on the lift value Z c For the middle length The codeword bits are divided into sub-blocks to obtain N. sub Each block;

[0671] According to the predefined sub-block interleaving pattern, N is processed... sub Each sub-block is interleaved to obtain a sub-block interleaved sequence.

[0672] In one embodiment, based on the boost value Z c For the middle length The codeword bits are divided into sub-blocks to obtain N. sub Each sub-block includes:

[0673] With the increase value Z c For the order of sub-block size, adjust the middle length The codeword bits are divided into sub-blocks to obtain N. sub There are 10 sub-blocks; the length of each sub-block is equal to the lift value Z. c .

[0674] In one embodiment, the sub-block interleaving pattern is composed of 0, 1, 2, ..., N sub -1 is composed of, and N sub The integers are a sequence arranged in a predefined interleaving order.

[0675] In one embodiment, sub-block interleaving involves interleaving all sub-blocks according to a predefined sub-block interleaving pattern.

[0676] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0677] It is obtained from the modulation order and the number of sub-blocks corresponding to the transmission block;

[0678] It is obtained from the modulation order, number of sub-blocks and basic graph index corresponding to the transport block.

[0679] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0680] It is determined based on the MCS index of the modulation and coding scheme corresponding to the transport block;

[0681] It is determined based on the MCS index set corresponding to the transport block, wherein the MCS index set includes at least two adjacent MCS indices in an MCS table;

[0682] It is determined based on the MCS index, the MCS index set, and the modulation order corresponding to the transport block;

[0683] It is determined based on the MCS index and transport layer number corresponding to the transport block;

[0684] It is determined based on the MCS index corresponding to the transport block, the transport layer number, and the number of resource elements in each transport block.

[0685] In one embodiment, the method for determining the sub-block interlacing pattern includes at least one of the following:

[0686] It is determined based on the coding rate, coding rate range, and modulation order of the transport block;

[0687] It is determined based on the current transmission redundancy version corresponding to the transmission block;

[0688] It is determined based on the current transmission redundancy version corresponding to the transport block, the system bit puncturing situation, the modulation order, and the coding rate.

[0689] In one embodiment, the predefined condition information includes at least one of the following: modulation order, sequence length of bit selection sequence and boost value; code rate and preset code rate threshold; code rate, preset code rate threshold and modulation order; modulation order and preset set of modulation order parameters for supporting sub-block interleaving; preset set of parameters for code rate and modulation order and preset code rate threshold.

[0690] In one embodiment, the predefined condition information includes at least one of the following: higher-level configuration signaling and MCS index of the MCS table; higher-level configuration signaling, MCS index, first preset MCS index set and second preset MCS index set of the MCS table; number of code blocks; number of code blocks and preset code block number threshold; transport block size; transport block size and preset transport block size threshold.

[0691] In one embodiment, the predefined condition information includes at least one of the following: higher-layer configuration enable signaling; higher-layer configuration enable signaling and predefined interleaving enable conditions; control information format; control information format and sub-block interleaving enable conditions; wireless network temporary identifier; search space.

[0692] In one embodiment, the signal processing apparatus further includes:

[0693] The processing unit 1010 is also configured to concatenate the code block interleaving sequence to obtain the concatenated codeword sequence.

[0694] In one embodiment, code block concatenation is performed on the code block interleaving sequence to obtain a concatenated codeword sequence, including one of the following:

[0695] The code block interleaving sequence is concatenated in order to obtain the concatenated codeword sequence;

[0696] The code block interleaving sequence is divided into multiple sets of code block interleaving sequences. Each code block interleaving sequence is interleaved and concatenated to obtain the corresponding interleaved and concatenated bit sequences. The interleaved and concatenated bit sequences are then concatenated in sequence to obtain the concatenated codeword sequence.

[0697] In one embodiment, the signal processing apparatus further includes:

[0698] The processing unit 1010 is also configured to scramble the control and multiplexed codeword sequence to obtain a scrambled sequence.

[0699] The modulation order of the scrambled sequence is Q. m The modulation mapping yields a sequence of modulation symbols for a codeword stream;

[0700] Map the modulation symbol sequence of the codeword stream to N L There are N transport layers. L Greater than or equal to 1;

[0701] If transform precoding is enabled, for N L The layer modulated symbol sequence is transformed and precoded to obtain N. L Layered complex number symbol sequence;

[0702] Map the complex symbol sequence of each transmission layer to one or more antenna ports;

[0703] Map the complex symbol sequence of each antenna port to a resource element;

[0704] OFDM waveform generation is performed on the complex symbol sequence on the resource unit to obtain the time-domain OFDM waveform.

[0705] The signal processing device provided in this embodiment is configured to achieve... Figure 4 The signal processing method applied to the transmitting end in the illustrated embodiment is similar in principle and technical effect to the signal processing device provided in this embodiment, and will not be described again here.

[0706] In one embodiment, Figure 11 This is a schematic diagram of a signal deprocessing apparatus provided in an embodiment of this application. The apparatus 1100 includes a processing unit 1110. The processing unit 1110 is used to perform the actions described in the embodiments of the signal deprocessing method, wherein the signal processing method includes all previously protected data features.

[0707] Processing unit 1110 is configured to perform decode block interleaving on the soft bit sequence of the code block to obtain a deinterleaved soft codeword sequence;

[0708] The deinterleaved soft codeword sequence is deselected to obtain the mother codeword;

[0709] LDPC decoding is performed on the mother codeword to obtain the decoded code block;

[0710] The decoded code block is segmented and verified to obtain the added transport block;

[0711] The added transport block is de-verified to obtain the transport block;

[0712] Specifically, it is determined whether the decoding block interleaving supports sub-block deinterleaving based on predefined condition information.

[0713] The signal demodulation device provided in this embodiment is configured to achieve... Figure 7 The signal deprocessing method applied to the receiving end in the illustrated embodiment is similar in principle and technical effect to the signal deprocessing device provided in this embodiment, and will not be described again here.

[0714] In one embodiment, the processing unit 1110 is further configured to perform decode block interleaving on the code block soft bit sequence to obtain a deinterleaved soft codeword sequence;

[0715] The deinterleaved soft codeword sequence is deselected to obtain the mother codeword;

[0716] LDPC decoding is performed on the mother codeword to obtain the decoded code block;

[0717] The decoded code block is segmented and verified to obtain the added transport block;

[0718] The added transport block is de-verified to obtain the transport block;

[0719] Among them, the determination of whether the deinterleaving bit selection supports sub-block deinterleaving is based on predefined condition information.

[0720] The signal demodulation device provided in this embodiment is configured to achieve... Figure 8 The signal deprocessing method applied to the receiving end in the illustrated embodiment is similar in principle and technical effect to the signal deprocessing device provided in this embodiment, and will not be described again here.

[0721] Those skilled in the art will clearly understand that the specific working process and technical effects of the device and unit described above, as well as the execution steps, can be referred to the description in the corresponding method embodiments above. For the sake of brevity, they will not be repeated here.

[0722] The aforementioned signal processing device and de-signal processing device can be a single chip. The processing unit can be implemented in hardware or software. When implemented in hardware, the processing unit can be a logic circuit, integrated circuit, etc. When implemented in software, the processing unit can be a general-purpose processor that reads software code stored in a storage unit. This storage unit can be integrated into the processor or located outside the processor and exist independently.

[0723] In one embodiment, Figure 12 This is a schematic diagram of the structure of a wireless communication transmitting device provided in an embodiment of this application. Figure 12 An example of a general wireless transmitting device is given, which includes at least a controller / processor 1210 implementing layer 2 / 3 functions, a processor 1220 implementing layer 1 functions, and a Tx transmitter 1230 for converting baseband signals to radio frequency signals and processing radio frequency signals. This device can be used for transmission from a base station or terminal. It should be noted that the processor is mainly used to process communication protocols and communication data, control the entire terminal device, execute software programs, and process the data in the software programs. In addition, the wireless transmitting device may also include input and output devices, such as touchscreens, displays, and keyboards, mainly used to receive user input data and output data to the user.

[0724] If the transmitting device is a terminal UE, the processor can read the software program from the storage unit, interpret and execute the instructions of the software program, and process the data in the software program. When data needs to be transmitted wirelessly, the processor performs baseband processing on the data to be transmitted, and then outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit performs RF processing on the baseband signal, and then transmits the RF signal to the outside in the form of electromagnetic waves through the antenna.

[0725] Specifically, this controller / processor 1210 implements Layer 3 and Layer 2 functions. In the DL (Data Link Controller), IP packets from the core network can be provided to a controller / processor. Layer 3 includes the Radio Resource Control (RRC) layer, and Layer 2 includes the Packet Data Convergence Protocol (PDCP), Radio Link Control (RLC), and Media Access Control (MAC) layers, primarily comprising the following four functions:

[0726] First, the controller / processor 1210 provides RRC functionality, which is responsible for managing the connection, resource allocation, handover, system information broadcasting, measurement reporting, power consumption control, and security management between user equipment and the radio access network. This ensures efficient connection, signal quality, and network resource optimization for the device, and dynamically adjusts between different states (such as RRC_IDLE, RRC_CONNECTED, and RRC_INACTIVE). It supports connection establishment, reconfiguration and release, handover management, system information broadcasting (such as MIB and SIB), as well as network slice selection and multi-connection management in 5G, ensuring that the network can flexibly respond to the needs of various application scenarios.

[0727] Secondly, the controller / processor 1210 also provides PDCP functionality, including header compression and decompression, security assurance (including encryption, decryption, integrity protection and verification), data segmentation and reassembly, and supports the continuity of data transmission during switching, ensuring efficient, secure and seamless uplink and downlink data transmission.

[0728] Third, the controller / processor 1210 also provides RLC layer functions, mainly including data segmentation, reassembly, retransmission, and order management between the physical layer and the PDCP layer, ensuring ordered transmission and retransmission of lost data packets. RLC supports three operating modes: Transparent Mode (TM), Unreliable Mode (UM), and Reliable Mode (AM), each optimized according to transmission reliability requirements. RLC is also responsible for data encapsulation and transmission control, ensuring data stability on the wireless link. In AM mode, RLC provides an Automatic Repeat Request (ARQ) mechanism to guarantee reliable data transmission and handle packet loss. In UM mode, RLC provides more efficient transmission but does not guarantee data reliability. RLC also adapts to different data packet size requirements through segmentation and reassembly functions to achieve efficient data transmission.

[0729] Fourth, the controller / processor 1210 also provides MAC layer functionality, acting as a bridge between the RLC layer and the physical layer. It is responsible for mapping logical channels to corresponding transmission channels, ensuring on-demand data transmission. The MAC layer controls data transmission based on network scheduling information, handles HARQ (Hybrid Automatic Repeat Request) retransmission processes, and manages resources such as transmission time slots, spectrum, and power. It dynamically adjusts the data transmission rate according to different QoS requirements and ensures that different services are prioritized. The MAC layer is also responsible for channel coding and modulation selection, ensuring reliable transmission under different channel conditions. Furthermore, the MAC layer processes different priority traffic on logical channels through priority scheduling, ensuring that high-priority traffic (such as control signaling or urgent data) is transmitted in a timely manner. Through efficient resource scheduling, logical channel priority processing and management, the MAC layer optimizes the utilization of wireless resources, ensuring the reliability, efficiency, and fairness of data transmission.

[0730] The transmit (TX) processor 1220 implements Layer 1 functions related to various signal processing functions. Layer 1 includes baseband processing at the physical (PHY) layer, including at least error detection, forward error correction (FEC) coding, interleaving, rate matching, mapping to the physical channel, modulation of the physical channel, and MIMO antenna processing. The TX processor processes the mapping of signal constellation diagrams based on various modulation schemes. The coded and modulated symbols can then be split into parallel streams. Each stream can then be mapped to OFDM subcarriers, multiplexed with a reference signal in the time and / or frequency domains, and then combined using an inverse fast Fourier transform (IFFT) to produce a physical channel carrying a stream of time-domain OFDM symbols. The OFDM streams are spatially pre-coded to generate multiple spatial streams.

[0731] Multiple spatial streams are supplied to different antennas 1250 via transmitter 1240TX, primarily involving intermediate frequency (IF) and radio frequency (RF) processing. Each transmitter 440TX can modulate an RF carrier with a corresponding spatial stream for transmission.

[0732] The controller / processor 1210 may be associated with the memory 1230 that stores program code and data.

[0733] If the transmitting device is a terminal, the processor can be used to support the terminal device in performing the actions described in the above-described signal processing method embodiments. The transmitter and transmitting antenna are used to support the terminal device in performing the transmission function as described in the transmission method.

[0734] If the transmitting device is a base station, the processor can be used to control the base station device to perform the actions described in the above-described signal processing method embodiments, and the transmitter and transmitting antenna are used to support the base station device in performing the transmission function as described in the transmission method.

[0735] In one embodiment, Figure 13 This is a schematic diagram of the structure of a wireless communication receiving device provided in an embodiment of this application. Figure 13 An example of a general wireless receiving device is given, which can be used for receiving signals from a terminal or a base station. If the receiving device is a terminal UE, when data is transmitted to the terminal device, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor. The processor converts the baseband signal into data and processes it.

[0736] In a wireless receiving device, such as the UE in the following example, each receiver 1340RX receives signals through its respective antenna 1350. Each receiver 1340RX recovers the information modulated onto the RF carrier and provides the information to the receive (RX) processor 1320. The RX processor 1320 implements Layer 1 functions related to various signal processing functions. The RX processor 1320 can perform spatial processing on the information to recover any spatial streams sent to the receiving device (such as the UE in the following example). If the destination of multiple spatial streams is the communication receiving device (such as the UE in the following example), they can be combined by the RX processor 1320 into a single OFDM symbol stream. The RX processor 1320 then uses a Fast Fourier Transform (FFT) to convert the OFDM symbol stream from the time domain to the frequency domain. The frequency domain signal consists of a separate OFDM symbol stream for each subcarrier of the OFDM signal. The symbols and reference signals on each subcarrier are recovered and demodulated by determining the most probable signal constellation point. These soft decisions may be based on channel estimation. The soft decisions are then decoded to recover the data and control signals originally transmitted by the transmitting device on the physical channel. The data and control signals are then provided to the controller / processor 1310, which implements the functions of the third layer and the second layer.

[0737] Memory 1330 may be referred to as computer-readable medium. In UL, controller / processor 1310 provides demultiplexing, packet reassembly, decryption, header decompression, and control signal processing between transport and logical channels to recover IP packets from the core network. Controller / processor 1310 is also responsible for error detection using ACK and / or NACK protocols to support HARQ operation.

[0738] Similar to the functions described in DL transmissions via the transmitting device, the controller / processor 1310 provides the associated RRC layer functions, PDCP layer functions, RLC layer functions, and MAC layer functions as previously described.

[0739] The controller / processor 1310 may be associated with a memory 1330 that stores program code and data. The memory 1330 may be referred to as a computer-readable medium.

[0740] If the transmitting device is a terminal, the processor can be used to support the terminal device in performing the actions described in the embodiments of the above signal deprocessing method, and the transmitter and transmitting antenna are used to support the terminal device in performing the transmitting function as described in the transmitting method.

[0741] If the transmitting device is a base station, the processor can be used to control the base station device to perform the actions described in the embodiments of the above signal demodulation method, and the transmitter and transmitting antenna are used to support the base station device to perform the transmission function as described in the transmission method.

[0742] Those skilled in the art will understand that, for ease of explanation, Figure 12 and Figure 13 In actual terminal devices, memory 1230 or 1330 may have multiple memories, and processor 1220 or 1320 may have multiple processors. Memory can also be called storage medium or storage device, etc.

[0743] For wireless communication systems, especially mobile communication systems, base stations are responsible for downlink transmission and uplink reception. A base station may include one or more radio frequency units (e.g., Remote Radio Units, RRUs) and one or more baseband units (BBUs, also known as Digital Units, DUs). This approach allows for separation of the baseband and radio frequency sections, enabling centralized control of the baseband section and allowing the radio frequency section to be located further away from the user, thus significantly improving coverage and reducing power consumption. For example, an RRU typically includes at least one transmit antenna 1240 and a transmitter 1250, and at least one receive antenna 1340 and a transmitter 1350. It should be noted that the transceiver units can be integrated or implemented using the same module. A BBU typically includes a controller / processor 1210, a Tx processor 1220, a controller / processor 1310, and an Rx processor 1320. Again, the control or processing of the transceiver can be integrated or implemented using the same module.

[0744] It should be noted that in the aforementioned communication transmitting and / or receiving devices, the processor can be a general-purpose processor or a dedicated processor, etc. For example, it can be a baseband processor or a central processing unit (CPU). A baseband processor can be used to process communication protocols and communication data, while a CPU can be used to control communication devices (e.g., base stations, terminals, or chips), execute software programs, and process data from the software programs. The communication device may include a transceiver unit for implementing signal input (reception) and output (transmission). For example, the communication device can be a chip, and the transceiver unit can be the chip's input and / or output circuits, or a communication interface. This chip can be used in a terminal, base station, or other communication device. Furthermore, if the communication device is a terminal, base station, or other communication device, the transceiver unit may include a transceiver, an RF chip, a filter, an analog-to-digital converter, an RF switch, etc.

[0745] In this application, the foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit all aspects to the precise form disclosed. Modifications and alterations can be made based on the foregoing disclosure, and can also be derived from practice in these areas.

[0746] In this application, no element, action, or instruction used herein should be construed as critical or necessary unless explicitly described. Furthermore, the articles “a” and “an” used herein are intended to include one or more items and may be used interchangeably with “one or more.” Additionally, the terms “set” and “group” used herein are intended to include one or more elements (e.g., related elements, unrelated elements, combinations of related and unrelated elements, and / or similar elements) and may be used interchangeably with “one or more.” If only one item is intended to be used, the phrase “single,” “only one,” or similar language is used.

[0747] In this application, the term "based on" should not be construed as a reference to a closed set of information, one or more conditions, one or more factors, or similar content. In other words, the phrase "based on A" (where "A" can be information, conditions, factors, etc.) should be construed as "at least based on A," unless specifically interpreted differently.

[0748] In this application, although specific combinations of features are referenced in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of aspects. In fact, many of these features may be combined in ways not specifically referenced in the claims and / or not closed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of aspects includes a combination of each dependent claim with all other claims in the claim set. The phrase “at least one” in the list of referenced items refers to any combination of these items, including individual members. For example, “comprising at least one of: A, B, or C” is intended to cover A, B, C, A and B, A and C, B and C, A and B and C (and any other order of A, B, and C).

[0749] In this application, the terms "system" and "network" are used interchangeably. The term "and / or" in this document is simply an association to describe the associated objects, indicating that there can be three relationships, such as A and / or B, which can represent three cases: A exists alone, A and B exist simultaneously, and A and B exist independently of B.

[0750] In this application, “when…”, “if” and “if” all indicate that the UE or base station will make corresponding processing under certain objective circumstances, rather than within a limited time. They do not require the UE or base station to make a judgment action during implementation, and do not imply any other restrictions.

[0751] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical units; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as processors, such as software executed by digital signal processors or microprocessors, or as hardware, or as integrated circuits, such as application-specific integrated circuits (ASICs). Such software can be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0752] As is known to those skilled in the art, the processor in this embodiment of the application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by hardware integrated logic circuits in the processor or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. A general-purpose processor can be a microprocessor, or any conventional processor or something similar. The steps of the methods disclosed in the various embodiments of this application can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other storage media mature in the art. The storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0753] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable eraseable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which acts as an external cache. For example, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM, SDRAM, double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchronous link DRAM, SLDRAM), and direct memory bus RAM (DR RAM). Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0754] This application also provides a computer-readable medium storing a computer program that, when executed by a computer, performs the function of any one of the aforementioned signal processing method embodiments or signal deprocessing method embodiments.

[0755] This application also provides a computer program product that, when executed by a computer, implements any one of the functions in the above-described signal processing method embodiments or signal deprocessing method embodiments.

[0756] Those skilled in the art can realize that the units and algorithm steps of each embodiment described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the differences in hardware and software interchangeability, the above description generally describes the composition and steps of each embodiment in terms of functionality. Whether these functions are implemented in hardware or software depends on the specific application and design limitations of the technical solution. A skilled craftsman can implement the described functions using different methods for each specific application, but such implementations should not be considered as exceeding the scope of that application.

[0757] In this application, the systems and / or methods described can be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not limited to any particular aspect. Therefore, this document describes the operation and behavior of the systems and / or methods without reference to any specific software code—it can be understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0758] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A signal processing method, characterized in that, The method includes: Add a CRC bit sequence to the transport block to obtain the transport block with the added bits. The added transmission block is sequentially segmented into code blocks and CRC bit sequences are added to obtain the code block bit sequence; Each bit sequence of the code block is LDPC encoded to obtain the mother codeword; Perform bit selection on each of the mother codewords to obtain a bit selection sequence; Each bit selection sequence is interleaved with code blocks to obtain a code block interleaved sequence; Specifically, it is determined whether the code block interleaving supports sub-block interleaving based on predefined condition information.

2. The method according to claim 1, characterized in that, Each bit selection sequence is subjected to code block interleaving to obtain a code block interleaved sequence, including: If the code block interleaving supports sub-block interleaving, the bit selection sequence is sub-block interleaved based on the number of sub-blocks to obtain a sub-block interleaved sequence, and the sub-block interleaved sequence is bit interleaved based on the modulation order to obtain a code block interleaved sequence. If the code block interleaving does not support sub-block interleaving, the bit selection sequence is bit interleaved based on the modulation order to obtain the code block interleaving sequence.

3. The method according to claim 2, characterized in that, The sub-block interleaving of the bit selection sequence based on the number of sub-blocks to obtain the sub-block interleaved sequence includes: The number of sub-blocks is determined based on the sequence length and boost value of the bit selection sequence; The bit selection sequence is interleaved with sub-blocks according to the number of sub-blocks to obtain a sub-block interleaved sequence.

4. The method according to claim 2, characterized in that, The sub-block interleaving of the bit selection sequence based on the number of sub-blocks to obtain the sub-block interleaved sequence includes: The number of sub-blocks is determined based on the sequence length and boost value of the bit selection sequence; The bit selection sequence is divided into sub-blocks based on the boost value to obtain multiple sub-blocks; The multiple sub-blocks are interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence.

5. The method according to claim 4, characterized in that, The step of dividing the bit selection sequence into sub-blocks based on the boost value to obtain multiple sub-blocks includes: The bit selection sequence is sub-blocked in sequence with the promotion value Zc as a sub-block size, to obtain N sub sub-blocks; wherein the N sub sub-blocks contain N sub -1 code blocks with a sub-block length equal to the promotion value Zc, and the last code block with a sub-block length less than or equal to the promotion value Zc.

6. The method according to claim 4, characterized in that, The sub-block interleaving pattern is a sequence arranged according to a predefined interleaving order; and the number of values ​​of the sub-block interleaving pattern is equal to the number of sub-blocks obtained by sub-block division, or the number of values ​​of the sub-block interleaving pattern is greater than the number of sub-blocks obtained by sub-block division.

7. The method according to claim 6, characterized in that, The sub-block interleaving pattern consists of 0, 1, 2,..., N sub -1 and the N sub integers are a sequence arranged in a predefined interleaving order.

8. The method according to claim 2, characterized in that, The sub-block interleaving of the bit selection sequence based on the number of sub-blocks to obtain the sub-block interleaved sequence includes: According to the sequence length E of the bit selection sequence r And the number of sub-blocks N is determined by the lifting value Zc sub Where r is the code block index. The bit selection sequence is sub-blocked according to the lifting value Zc, and N sub sub-blocks are obtained. If the length of the last sub-block is equal to the lifting value Zc, the N sub-blocks are sub-block interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaved sequence. sub If the length of the last sub-block is equal to the lifting value Zc, the N sub-blocks are sub-block interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaved sequence. If the length of the last sub-block is less than the lifting value Zc, the N sub -1 sub-blocks except the last sub-block are sub-block interleaved according to a predefined sub-block interleaving pattern, leaving the last sub-block position unchanged, resulting in a sub-block interleaved sequence.

9. The method according to claim 2, characterized in that, The sub-block interleaving of the bit selection sequence based on the number of sub-blocks to obtain the sub-block interleaved sequence includes: According to the sequence length E of the bit selection sequence r And the promotion value Zc determines the number of sub-blocks N sub ; The bit selection sequence is sub-blocked according to the lifting value Zc, and N sub sub-blocks are obtained. sub-block interleaving the N sub sub-blocks according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence; wherein the sub-block interleaving pattern is composed of 0, 1, 2, …, N sub -1, and the N sub integers are preset arranged according to a predefined interleaving order, and the last number of the sub-block interleaving pattern is N sub -1.

10. The method according to any one of claims 4-6, characterized in that, Between sub-block partitioning and sub-block interleaving, if the length of the last sub-block among all sub-blocks after sub-block partitioning is less than the boost value, the last sub-block is bit-padded so that the length of the last sub-block is equal to the boost value.

11. The method according to any one of claims 4-6, characterized in that, Before sub-block partitioning, if the rate-matched length of each code block is not an integer multiple of the boost value, bit padding is performed on the rate-matched sequence of each code block by adding Zc*ceil(E). r / Zc)-E r Fill in bits such that the bit-filled sequence is an integer multiple of the boost value.

12. The method according to claim 10, characterized in that, The bit stuffing of the last sub-block includes one of the following: filling Zc*ceil(E r / Zc)-E r placeholders, where ceil denotes rounding up. Zc*ceil(E r / Zc)-E r empty bit symbols.

13. The method according to claim 10, characterized in that, The step of performing sub-block interleaving on the multiple sub-blocks according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence includes: Sub-blocks of size 'lift' are interleaved according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence.

14. The method according to claim 10, characterized in that, After performing sub-block interleaving on the plurality of sub-blocks according to a predefined sub-block interleaving pattern to obtain a sub-block interleaving sequence, the method further includes: Remove the padding bits contained in the sub-block interleaving sequence.

15. The method according to claim 1, characterized in that, Each bit selection sequence is subjected to code block interleaving to obtain a code block interleaved sequence, including: If the code block interleaving supports sub-block interleaving, the input index sequence corresponding to the bit selection sequence is interleaved based on the number of sub-blocks to obtain a first interleaving index, and bit interleaving is performed on the first interleaving index based on the modulation order to obtain a second interleaving index. The bit selection sequence is then mapped bit-to-bit interleaving according to the second interleaving index. If the code block interleaving does not support sub-block interleaving, bit interleaving is performed on the input index sequence corresponding to the bit selection sequence based on the modulation order to obtain a third interleaving index, and bit selection sequence is mapped bit by bit according to the third interleaving index.

16. The method according to claim 1, characterized in that, The step of performing code block interleaving on each of the bit selection sequences to obtain a code block interleaved sequence includes: If the code block interleaving supports sub-block interleaving, the bit selection sequence is interleaved according to the second interleaving index to obtain a code block interleaving sequence; wherein, the second interleaving index is determined based on the sub-block interleaving based on the first interleaving index, the boost value and the sub-block interleaving pattern, the first interleaving index is determined based on the bit interleaving based on the modulation order, and the second interleaving index is a first function of the output index of the code block interleaving sequence; If the code block interleaving does not support sub-block interleaving, the bit selection sequence is interleaved according to the third interleaving index to obtain a code block interleaving sequence; wherein, the third interleaving index is determined based on the bit interleaving of the modulation order, and the third interleaving index is a second function of the output index of the code block interleaving sequence.

17. The method according to claim 15 or 16, characterized in that, Before determining the first interleaving index based on the modulation order bit interleaving, the method further includes: The bit selection sequence is bit-padded so that the length of each sub-block is equal to the boost value.

18. The method according to claim 15 or 16, characterized in that, After performing code block interleaving on the bit selection sequence according to the second interleaving index to obtain the bit interleaved sequence, the method further includes: Remove the padding bits contained in the sub-block interleaving sequence.

19. The method according to any one of claims 4-8, characterized in that, The method for determining the sub-block interlacing pattern includes at least one of the following: It is obtained based on the modulation order and the number of sub-blocks corresponding to the transmission block; It is obtained based on the modulation order, number of sub-blocks, and basic graph index corresponding to the transport block.

20. The method according to any one of claims 4-8, characterized in that, The method for determining the sub-block interlacing pattern includes at least one of the following: It is determined based on the Modulation and Coding Scheme (MCS) index corresponding to the transport block; The MCS index set corresponding to the transport block is determined, wherein the MCS index set includes at least two adjacent MCS indices in an MCS table; It is determined based on the MCS index, MCS index set, and modulation order corresponding to the transport block; It is determined based on the MCS index and transport layer number corresponding to the transport block; The number of transport blocks is determined based on the MCS index corresponding to the transport block, the transport layer number, and the number of resource elements in each transport block.

21. The method according to any one of claims 4-8, characterized in that, The method for determining the sub-block interlacing pattern includes at least one of the following: It is determined based on the coding rate, coding rate range, and modulation order of the transport block; It is determined based on the current transmission redundancy version corresponding to the transmission block; The value is determined based on the current transmission redundancy version corresponding to the transmission block, the system bit puncturing situation, the modulation order, and the coding rate.

22. The method according to claim 1, characterized in that, The predefined condition information includes at least one of the following: Modulation order, bit selection sequence length, and boost value; Bitrate and preset bitrate threshold; Bit rate, preset bit rate threshold, and modulation order; The modulation order and the preset set of modulation order parameters for supporting sub-block interleaving; A set of preset parameters for bit rate and modulation order, and a preset bit rate threshold.

23. The method according to claim 1, characterized in that, The predefined condition information includes at least one of the following: High-level configuration signaling and MCS indexes in MCS tables; MCS table high-level configuration signaling, MCS index, first preset MCS index set and second preset MCS index set; Number of code blocks; Number of code blocks and preset number of code blocks threshold; Transfer block size; Transport block size and preset transport block size threshold.

24. The method according to claim 1, characterized in that, The predefined condition information includes at least one of the following: High-level configuration enable signaling; High-level configuration enables signaling and predefined interleaved enable scenarios; Control information format; Control information format and sub-block interleaving enable status; Temporary identifier for wireless network; Search space.

25. The method according to claim 1, characterized in that, The method further includes: The code block interleaving sequence is concatenated to obtain the concatenated codeword sequence.

26. The method according to claim 24, characterized in that, The concatenation of the code block interleaving sequence to obtain the concatenated codeword sequence includes one of the following: The code block interleaving sequence is concatenated in order to obtain the concatenated codeword sequence; The code block interleaving sequence is divided into multiple sets of code block interleaving sequences, and each code block interleaving sequence is interleaved and concatenated to obtain the corresponding interleaved and concatenated bit sequences. The interleaved and concatenated bit sequences are then concatenated in sequence to obtain the concatenated codeword sequence.

27. The method according to claim 25 or 26, characterized in that, Also includes: The controlled and multiplexed codeword sequence is scrambled to obtain a scrambled sequence. modulating the scrambled sequence with a modulation order Q m to obtain a sequence of modulation symbols of a codeword stream; mapping a sequence of modulation symbols of the codeword stream to N L transmission layers, N L is greater than or equal to 1; If transform precoding is enabled, the N L layer modulation symbol sequences are transform precoded to obtain N L layer complex symbol sequences; Map the complex symbol sequence of each transmission layer to one or more antenna ports; Map the complex symbol sequence of each antenna port to a resource element; OFDM waveform generation is performed on the complex symbol sequence on the resource unit to obtain the time-domain OFDM waveform.

28. A signal processing method, characterized in that, The method includes: Add a CRC bit sequence to the transport block to obtain the transport block with the added bits. The added transmission block is sequentially segmented into code blocks and CRC bit sequences are added to obtain the code block bit sequence; Each bit sequence of the code block is LDPC encoded to obtain the mother codeword; Perform bit selection on each of the mother codewords to obtain a bit selection sequence; Each bit selection sequence is interleaved with code blocks to obtain a code block interleaved sequence; Specifically, the bit selection is determined based on predefined condition information to determine whether sub-block interleaving is supported.

29. The method according to claim 28, characterized in that, The step of performing bit selection on each of the mother codewords to obtain a bit selection sequence includes: If the bit selection supports sub-block interleaving, bit selection based on bit interleaving is performed on the mother codeword to obtain a bit selection sequence; If the bit selection does not support sub-block interleaving, bit selection is performed on the mother codeword to obtain a bit selection sequence.

30. The method according to claim 29, characterized in that, The step of performing bit selection based on bit interleaving on the mother codeword to obtain a bit selection sequence includes: Determine the final length E of the bit selection for each code block. r and middle length Select from the mother codewords One codeword bit; Regarding the Each codeword bit is interleaved into a sub-block to obtain a sub-block interleaved sequence; From length Select E from the sub-block interleaving sequence r Each codeword bit is used as a bit selection sequence.

31. The method according to claim 30, characterized in that, The bit selection final length E r According to the total number of coded bits G of the transport block, the modulation order Qm, and the number of transmission layers N L is determined.

32. The method according to claim 30, characterized in that, The intermediate length The final length and boost value Z are selected based on the bits. c It has been confirmed.

33. The method according to claim 30, characterized in that, The intermediate length 34. The method according to claim 30, characterized in that, The above Each codeword bit is interleaved into sub-blocks to obtain an interleaved sub-block sequence, including: Based on the middle length and the increase value Z c Determine the number of sub-blocks N sub ; Based on the lift value Z c For the intermediate length The codeword bits are divided into sub-blocks to obtain N. sub Each block; According to the predefined sub-block interleaving pattern, the N is... sub Each sub-block is interleaved to obtain a sub-block interleaved sequence.

35. The method according to claim 34, characterized in that, The increase value Z c For the intermediate length The codeword bits are divided into sub-blocks to obtain N. sub Each sub-block includes: With the increase value Z c For the order of sub-block size, relative to the intermediate length The codeword bits are divided into sub-blocks to obtain N. sub There are 10 sub-blocks; the length of each sub-block is equal to the lift value Z. c .

36. The method according to claim 34, characterized in that, The sub-block interlacing pattern is composed of 0, 1, 2, ..., N. sub -1 constitutes, and the N sub The integers are a sequence arranged in a predefined interleaving order.

37. The method according to claim 34, characterized in that, The sub-block interleaving process involves interleaving all sub-blocks according to a predefined sub-block interleaving pattern.

38. The method according to any one of claims 34-37, characterized in that, The method for determining the sub-block interlacing pattern includes at least one of the following: It is obtained based on the modulation order and the number of sub-blocks corresponding to the transmission block; It is obtained based on the modulation order, number of sub-blocks, and basic graph index corresponding to the transport block.

39. The method according to any one of claims 34-37, characterized in that, The method for determining the sub-block interlacing pattern includes at least one of the following: It is determined based on the Modulation and Coding Scheme (MCS) index corresponding to the transport block; The MCS index set corresponding to the transport block is determined, wherein the MCS index set includes at least two adjacent MCS indices in an MCS table; It is determined based on the MCS index, MCS index set, and modulation order corresponding to the transport block; It is determined based on the MCS index and transport layer number corresponding to the transport block; The number of transport blocks is determined based on the MCS index corresponding to the transport block, the transport layer number, and the number of resource elements in each transport block.

40. The method according to any one of claims 34-37, characterized in that, The method for determining the sub-block interlacing pattern includes at least one of the following: It is determined based on the coding rate, coding rate range, and modulation order of the transport block; It is determined based on the current transmission redundancy version corresponding to the transmission block; The value is determined based on the current transmission redundancy version corresponding to the transmission block, the system bit puncturing situation, the modulation order, and the coding rate.

41. The method according to claim 28, characterized in that, The predefined condition information includes at least one of the following: Modulation order, bit selection sequence length, and boost value; Bitrate and preset bitrate threshold; Bit rate, preset bit rate threshold, and modulation order; The modulation order and the preset set of modulation order parameters for supporting sub-block interleaving; A set of preset parameters for bit rate and modulation order, and a preset bit rate threshold.

42. The method according to claim 28, characterized in that, The predefined condition information includes at least one of the following: High-level configuration signaling and MCS indexes in MCS tables; MCS table high-level configuration signaling, MCS index, first preset MCS index set and second preset MCS index set; Number of code blocks; Number of code blocks and preset number of code blocks threshold; Transfer block size; Transport block size and preset transport block size threshold.

43. The method according to claim 28, characterized in that, The predefined condition information includes at least one of the following: High-level configuration enable signaling; High-level configuration enables signaling and predefined interleaved enable scenarios; Control information format; Control information format and sub-block interleaving enable status; Temporary identifier for wireless network; Search space.

44. The method according to claim 28, characterized in that, The method further includes: The code block interleaving sequence is concatenated to obtain the concatenated codeword sequence.

45. The method according to claim 44, characterized in that, The concatenation of the code block interleaving sequence to obtain the concatenated codeword sequence includes one of the following: The code block interleaving sequence is concatenated in order to obtain the concatenated codeword sequence; The code block interleaving sequence is divided into multiple sets of code block interleaving sequences, and each code block interleaving sequence is interleaved and concatenated to obtain the corresponding interleaved and concatenated bit sequences. The interleaved and concatenated bit sequences are then concatenated in sequence to obtain the concatenated codeword sequence.

46. ​​The method according to claim 44 or 45, characterized in that, Also includes: The controlled and multiplexed codeword sequence is scrambled to obtain a scrambled sequence. The modulation order of the scrambled sequence is Q. m The modulation mapping yields a sequence of modulation symbols for a codeword stream; Map the modulation symbol sequence of the codeword stream to N L There are N transport layers. L Greater than or equal to 1; If transform precoding is enabled, for N L The layer modulated symbol sequence is transformed and precoded to obtain N. L Layered complex number symbol sequence; Map the complex symbol sequence of each transmission layer to one or more antenna ports; Map the complex symbol sequence of each antenna port to a resource element; OFDM waveform generation is performed on the complex symbol sequence on the resource unit to obtain the time-domain OFDM waveform.

47. A signal deprocessing method, characterized in that, The method includes: The soft bit sequence of the code block is interleaved with the decoder block to obtain the deinterleaved soft codeword sequence; The deinterleaved soft codeword sequence is subjected to debit selection to obtain the mother codeword; The mother codeword is subjected to LDPC decoding to obtain the decoded code block; The decoded code block is segmented and verified to obtain the added transmission block; The added transport block is de-verified to obtain the transport block; Specifically, it is determined whether the decoding block interleaving supports sub-block deinterleaving based on predefined condition information.

48. A signal deprocessing method, characterized in that, The method includes: The soft bit sequence of the code block is interleaved with the decoder block to obtain the deinterleaved soft codeword sequence; The deinterleaved soft codeword sequence is subjected to debit selection to obtain the mother codeword; The mother codeword is subjected to LDPC decoding to obtain the decoded code block; The decoded code block is segmented and verified to obtain the added transmission block; The added transport block is de-verified to obtain the transport block; Specifically, the determination of whether the deinterleaving bit selection supports sub-block deinterleaving is based on predefined condition information.

49. A communication device, characterized in that, include: One or more processors; The one or more processors implement the method as described in any one of claims 1-27, 28-46, 47 or 48.

50. The communication device according to claim 49, characterized in that, Also includes: A memory; The memory is configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the signal processing method as described in any one of claims 1-27, 28-46, 47 or 48.

51. A storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1-27, 28-46, 47, or 48.

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