Frequency divider with reduced jitter and apparatus based thereon

Abstract

Apparatus (70) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1). The apparatus (70) comprises a chain of frequency dividing cells (71-76), wherein each of the frequency dividing cells (71-76) has a pre-defined division ratio and comprises a clock input (CKi) for receiving an input clock (CKin); a divided clock output (CKi+1)for providing an output clock (CKout) to a subsequent frequency dividing cell; a mode control input (MDi) for receiving a mode control input signal (MDin) from the subsequent frequency dividing cell; and a mode control output for providing a mode control output signal (MDout) to a preceding frequency dividing cell. The apparatus further comprises a latch (77) for altering the division ratio and - a D-Flip-Flop (50) circuitry with two latches (51, 52). The first latch (51) is clocked by a first signal (CK3) and the second latch (52) is clocked by a second signal (CK1), whereby the frequency of the first signal (CK3) is lower than the frequency of the second signal (CK1).

Description

technical field [0001] The present invention relates to frequency dividers and devices for frequency division. More specifically, the present invention relates to frequency divider structures and circuit techniques based on zip-chain frequency divider structures suitable for use in transmitters and receivers, in particular for radio frequency signal transmission. Background technique [0002] In recent years, much effort has been devoted to the radio frequency (RF) design of standard complementary metal oxide semiconductor (CMOS) single-chip transceivers. In particular, CMOS implementations of frequency dividers and frequency synthesizers, which are one of the key blocks making up transceivers, have attracted much attention. The most notable trends here are zip-chain divider architectures and so-called current-mode logic (CML). [0003] Known zip-chain dividers consist of chains of identical circuits that divide by 2 / 3 cells. figure 1 A traditional d...

AI Technical Summary

Problems solved by technology

[0012] Jitter is a major concern in frequency dividers, oscillators, frequency synthesizers, etc., because even a small amount of jitter introduced into these circuits can cause severe changes in its spectral and timing properties, resulting in lower signal-to-noise ratio, increased bit error rate, and higher interference to adjacent channels

Jitter is also important in clock-synchronized and sampled data systems, since zero-crossing points often contain information, so any uncertainty in switching times will cause errors

[0013] So far, spectral purity in general (and jitter accumulation in particular) has not been strictly considered when designing zip-chain divider circuits in the form of CML

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