Integrated semiconductor internal memory with formed network region selective transistor

Abstract

An integrated semiconductor memory having selection transistors can be formed at a web. The web can be arranged on an insulation layer. The first source / drain region can be arranged on the insulation layer at one lateral end of the web and the second source / drain region can be arranged on the insulation layer at another lateral end of the web. The longitudinal sides of the web and a top side of the web can be covered with a layer sequence including a gate dielectric and a gate electrode. High write-read currents can be achieved in the on state of the selection transistors and leakage currents occurring in the off state can be reduced.

Description

technical field [0001] The present invention relates to an integrated semiconductor memory comprising a memory cell having a storage capacitor and a selective transistor formed on a ridge made of semiconductor material and having first source / drain regions, a second source electrode / drain regions and at least one gate layer. Background technique [0002] An integrated semiconductor memory has a memory cell array including multiple memory cells for storing digital information, and a logic region for driving the memory cells and operating the semiconductor memory. The storage capacitor is driven through a selective transistor located at the intersection between a wordline and a bitline, and storage in the storage capacitor is affected by whether the transistor is electrically on or off. Additional transistors are provided in the logic region, the additional transistors of which are not used to select memory cells, as compared to selective transistors, which are constructed an...

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Problems solved by technology

[0007] The write and read speeds cannot be increased sufficiently to the desired extent considering the reduced operating voltage and the reduced size of the side of the memory cell with limited current density

[0008] In addition, leakage currents, in particular between the storage capacitor and the selector transistor, lead to an earlier-than-expected discharge of the storage capacitor (precisely in the case of electrically dependent semiconductor memories), which shortens the refresh rate. period as well as causing memory current consumption to rise

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