Word line driver of semiconductor memory device

A word line driver, storage device technology, applied in static memory, digital memory information, information storage, etc., can solve problems such as large space, loss of chip area, and difficulty in implementing negative voltage converters

Inactive Publication Date: 2003-01-22
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, negative voltage sources often occupy a large space in memory devices
Second, the complex implementation required for conventional negative wordline schemes typically has a die area penalty since each wordline requires a negative wordline driver
Also, it is difficult to implement a negative voltage converter within the pitch of the word line driver

Method used

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  • Word line driver of semiconductor memory device
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  • Word line driver of semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0033] attached Figure 4 Shown is a first embodiment of a memory device according to the invention. in the attached Figure 4 The drive circuit shown in is configured so that it keeps the word line WL at Vbb after the precharge operation, but diverts most of the word line discharge current to Vss, thereby reducing the need for a negative supply. attached Figure 4 The driver circuit of the present invention includes a power hold circuit (or “hold circuit”) 20 and a driver stage 18 with a modified driver section 22 . The hold circuit 20 includes an NMOS transistor M4 having a channel connected between WL and Vbb and a gate connected to the output of an inverter INV1 and a substrate connected to Vbb. Inverter INV1 is referenced to Vbb and has an input connected to a word line. In the modified driver section 22, a diode connecting the NMOS transistor M3 is connected in series with M2. The substrates of both M2 and M3 are connected to Vbb. The holding circuit 20 is preferab...

Embodiment 2

[0039] attached Figure 5 Shown is a second embodiment of a memory device according to the invention. in the attached Figure 5 The drive circuit shown in the attached Figure 4 The drive circuit differs in the attached Figure 5 No hold circuit is required in , and a further modification is made to the modified driver section 24, including a larger NMOS pull-down transistor M2. The source of M2 is connected to Vbb and the gate of M3 is connected together with the gate of M2 to the output of the row decoder. The channel of M4 is connected between the drain of M2 and Vss, and the gate of M4 is connected to the word line WL. The substrates of M2, M3 and M4 are all connected to Vbb. Thus, transistor M4 diverts the wordline discharge current to Vss by coupling the wordline to Vss in response to the wordline voltage whenever M3 is now on. Transistor M2 now couples the word line to Vbb in response to the row address information.

[0040] At the end of the access operation, th...

Embodiment 3

[0043] attached Figure 6 Shown is a third embodiment of a memory device according to the invention. in the attached Figure 6 The structure and operation of the drive circuit shown in the attached Figure 5 The structure and operation of the drive circuit is similar, but the transistor M3 has been changed to be in series with M4 instead of M2.

[0044] Sub word line drive scheme

[0045] The principles of the present invention discussed above with respect to memory devices having a main wordline scheme can be extended to other types of memory devices including, for example, memory devices utilizing sub-wordline driving schemes. attached Figure 7 Shown is the core structure of a typical prior art DRAM device utilizing a sub-word line driving scheme. Although memory devices of this type are disclosed in US Pat. Nos. 5,416,748, 5,596,542, 5,764,585, 5,781,498, and 5,986,966, memory devices of this type are briefly summarized here for convenience...

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Abstract

A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

Description

[0001] This application claims priority based on Provisional Application No. 60 / 288,744, filed May 4, 2001 by the same inventor as the present application, entitled "WORD LINE DRIVER FOR A SEMICODUCTOR MEMORY DEVICE ", which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates generally to semiconductor memory devices, and more particularly to word line driver circuits for semiconductor memory devices. Background technique [0003] attached figure 1 Shown is a memory cell in a typical DRAM memory device. The refresh time of such memory cells is reduced by two main types of leakage currents: the junction leakage current I caused by defects at the junction boundary of transistor M1 1 ; and the channel leakage current I caused by the sub-threshold current flowing through transistor M1 2 . The junction leakage current I can be reduced by reducing the channel implant...

Claims

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Application Information

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IPC IPC(8): G11C11/407G11C8/08G11C11/408
CPCG11C11/4085G11C8/08
Inventor 沈载润柳济焕
Owner SAMSUNG ELECTRONICS CO LTD
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