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Feedback control of strip time to reduce post strip critical dimension variation in transistor gate electrode

A gate and stripping technology, applied in the direction of program control, total factory control, electrical program control, etc., can solve the problems of device speed, leakage transistor performance parameter changes, reduced productivity, output, and profit, etc.

Inactive Publication Date: 2003-09-10
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Changes in the stripping ratio of the trench will directly lead to changes in the critical dimension of the gate
Variations in the critical dimensions of the gate will result in variations in device speed, leakage, and other transistor performance parameters
Typically, the added variability reduces productivity, output, and profits

Method used

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  • Feedback control of strip time to reduce post strip critical dimension variation in transistor gate electrode
  • Feedback control of strip time to reduce post strip critical dimension variation in transistor gate electrode
  • Feedback control of strip time to reduce post strip critical dimension variation in transistor gate electrode

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Embodiment Construction

[0015] Hereinafter, embodiments of the present invention will be described. In the interest of stylistic clarity, not all features of an actual application are described in this specification. Of course, it is hoped that in the development of such practical embodiments, the needs of various special applications must first be determined in order to achieve the inventor's special purpose, such as compatibility with related systems and related commercial constraints, which may vary with different applications. changed. Furthermore, it should be understood that although the result of this research and development is complicated and time-consuming, it will become no more than a routine work for those skilled in the art because of the disclosure of the present invention.

[0016] now refer to figure 1 , shows a simplified block diagram of a processing line 100 for processing wafers 110 provided in accordance with the present invention. The processing line 100 includes a pre-strip...

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Abstract

A method for decreasing variations in gate electrode widths is provided. The method includes providing a wafer having a ate electrode (230) formed thereon and an anti-reflective coating layer (240) formed over at least a portion of the gate electrode (230). The gate electrode (230) has a width. The width of the gate electrode (230) is measured. A strip rate for a strip tool (130) adapted to remove the anti-reflective coating (240) is determined. The measured width of the gate electrode (230) is compared to a target gate electrode critical dimension to determine an overetch time based on the strip rate. The operating recipe of the strip tool (130) is modified based on the overetch time. A processing line (100) includes a first metrology tool (120), a strip tool (130), and a process controller (150). The first metrology tool (120) is adapted to measure the width of a gate electrode (230) formed on a wafer. The gate electrode (230) has an anti-reflective coating layer (240) formed over at least a portion of the gate electrode (230). The strip tool (130) is adapted to remove the anti-reflective coating (240). The process controller (150) is adapted to determine a strip rate for the strip tool (130), compare the width of the gate electrode (230) to a target gate electrode critical dimension to determine an overetch time based on the strip rate, and modify the operating recipe of the strip tool (130) based on the overetch time.

Description

technical field [0001] The present invention relates to the field of semiconductor device fabrication, and more particularly to methods and apparatus for reducing post-stripping critical dimension variation on transistor gates using feedback control of stripping time. Background technique [0002] There is a continuing trend in semiconductor technology to manufacture more and / or faster semiconductor devices. This trend has enabled very large scale integration (ULSI) to continue to reduce the size and features of devices and circuits. For example, in integrated circuits with field effect transistors, a very important processing step is the formation of the gates for each transistor, where special attention is paid to the size of the gates. In many applications, performance characteristics (eg, switching speed) and dimensions of transistors are a function of the channel length of the device, which approximately corresponds to the width of the transistor gate. Thus, for examp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/418H01L21/28H01L21/306H01L21/311H01L21/3213H01L21/66H01L29/423H01L29/49H01L29/78
CPCH01L21/32134H01L21/31111H01L21/28026G05B19/41865H01L21/32139G05B2219/32096G05B2219/45031H01L22/20Y02P90/02H01L21/18
Inventor J·S·蓝斯佛得
Owner GLOBALFOUNDRIES INC
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