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CMOS component and preparation method

A manufacturing method and component technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve the problem of not being able to increase the driving current of PMOS transistors or NMOS transistors at the same time

Inactive Publication Date: 2004-05-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] Although the above method of using silicon nitride layer to generate stress to improve transistor performance is simpler than the method of using Si-Ge buffer layer, it can only be used to increase the driving current of PMOS transistor or NMOS transistor, and cannot improve PMOS transistor at the same time. or the steering current of an NMOS transistor

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Embodiment Construction

[0019] The present invention provides a structure of CMOS elements, such as Figure 3G As shown, its structure includes respectively disposing the PMOS transistor 304 and the NMOS transistor 302 in the n-well region NW and the p-well region PW of the substrate 300, and respectively disposing the compressive stress material layer 310a and the tensile stress material layer 320a in the PMOS transistor 304 surface and NMOS transistor 302 surface.

[0020] It should be noted that the material covering the PMOS transistor 304 can be a compressive stress material or a tensile stress material, and the compressive stress material layer 310a is taken as an example in this specification.

[0021] In addition, the compressive stress material layer 310a and the tensile stress material layer 320a cover at least the source and drain electrodes of the PMOS transistor 304 and the NMOS transistor 302 respectively. The tensile stress material layer 320 a covers the entire surface of the PMOS tr...

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Abstract

The invention relates to CMOS component. Structure of the CMOS includes: setting up material layer of compressive stress or pulling stress on surface of PMOS transistor, and setting up material layer of pulling stress on surface of NMOS transistor. The invention also discloses the method for manufacturing the said CMOS.

Description

technical field [0001] The present invention relates to a CMOS device and a manufacturing method thereof, in particular to a method and a structure thereof for increasing performance of a CMOS device by using local mechanical-stress control (LMC for short). Background technique [0002] In current semiconductor devices, silicon bulk (Si bulk) is used as the substrate, and the purpose of high-speed operation and low power consumption is achieved by reducing the size of the device. However, the current reduction in component size is approaching physical limits and cost limits. Therefore, it is necessary to develop technologies other than the method of downsizing in order to achieve high-speed operation and low power consumption. [0003] Therefore, it has been proposed to use stress control in the channel region of the transistor to overcome the limit of device miniaturization. This method increases the mobility of electrons and holes by changing the Si lattice spacing using...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L27/092
Inventor 黄健朝王昭雄葛崇祜胡正明
Owner TAIWAN SEMICON MFG CO LTD