Process for eliminating photoresist poison of photo-etching in integrated circuit manufacture technology

A photoresist and process technology, used in circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as insufficient development, increased heat in integrated circuits, and impact on integrated circuit performance, and eliminate photoresist poisoning. , the effect of improving yield

Inactive Publication Date: 2004-11-17

SHANGHAI HUA HONG GROUP +1

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AI-Extracted Technical Summary

Problems solved by technology

1. The circuit delay (RCdelay) caused by the increased capacitance of the rear interconnection has exceeded the delay of the front transistor and seriously affected the working speed of the integrated circuit

2. Due to the increase in capacitance, the power dissipation increases, which increases the heat emitted by the integrated cir...

Abstract

The invention belongs to semiconductor integrated circuit manufacturing technology field, which concretely refers to a process that can eliminate the drugged photoetching glue effection of carbon mingled silicon dioxide material (SiOC:HsiOC:H) in the Single Damascene photoetching process. A thin layer of SiO2 is deposited on the surface of SiOC:H with PECVD method, them carries on photoetching, and etching, in the post CMP process, the thin oxygen layer is eliminated.

Application Domain

Semiconductor/solid-state device manufacturing

Technology Topic

Thin layerIntegrated circuit manufacturing +6

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Experimental program(1)

Example Embodiment

[0017] specific implementation plan

[0018] Below further describe the present invention by specific embodiment:

[0019] 1. SiO2 2 Thin layers are deposited using plasma chemical vapor phase methods, such as the DxZ deposition chamber on the Centura system of Applied Materials, or the Eagle-10 system of ASM. The deposition is carried out at a suitable temperature (for example: 350° C. or 400° C.) by using a mixed gas containing silane and nitrogen and oxygen, the time is about 8 seconds or 10 seconds, and the gas pressure is about 5.5 Torr or 6.5 Torr.

[0020] 2. Hang coat DUV photoresist, expose and develop it.

[0021] 3. For SiO 2 Thin layers and SiOC:H materials are etched.

[0022] 4. After the deposition of the barrier layer and the electroplating of copper are completed, the thin oxygen layer is removed in the subsequent barrier layer CMP.

[0023] The present invention utilizes mature SiO 2 The production process (deposition, etching, CMP), which is applied to the integration of SiOC:H low dielectric material and Cu, successfully solves the problem of photoresist poisoning of SiOC:H material in SD process.

PUM

Property	Measurement	Unit
Deposition thickness	9.0 ~ 15.0	nm

Description & Claims & Application Information

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Classification and recommendation of technical efficacy words

Improve yield

Process for eliminating photoresist poison of photo-etching in integrated circuit manufacture technology

AI-Extracted Technical Summary

Problems solved by technology

Abstract

Image

Examples

Example Embodiment

PUM

Description & Claims & Application Information

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