Semiconductor memory module

Abstract

The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.

Description

technical field [0001] The present invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one column and at least one buffer chip, which drives and receives clock signals, command and address signals for the memory chips, and via a clock inside the module, address and command and data buses to and from memory chips, and it forms the interface to the external main memory bus. Background technique [0002] For extremely fast memory architectures with large integration, such as DDR-III DRAMs, "buffer chips" will be required in the future. Attached FIG. 8 illustrates such a memory system in which buffer chips 100 , 210 located in individual memory modules 100 , 200 are connected in series to a main memory bus 400 flowing to a memory controller 300 . On the buffer chips 110 , 210 , the switching device S ensures that data is only read from or written into the individual address memory module 100 or 200 . Roman numerals I, II, ...

AI Technical Summary

Problems solved by technology

[0006] The time delay in reading the data limits the maximum operating frequency below 800MHz (= 1.125ns), or needs to be compensated by complex circuitry in the buffer, which will create another delay in the data, since the oldest data may be delayed by at least 1.2 ns plus the processing time delay in the compensation circuit

Images