Decoding apparatus, communication apparatus and decoding method

Abstract

A decoding apparatus includes a branch metric calculation unit 32 for sequentially Viterbi-decoding a plurality of data sequences over respective data lengths from the start at the same time, an ACS (Add-Compare-Select) circuit 35 and a stop register 44 for sequentially comparing likelihoods of respective data sequences which were Viterbi-decoded at the same time and stopping said simultaneous decoding means from decoding respective data sequences if it is determined based upon compared results if a likelihood of a certain data sequence is lower than a predetermined threshold value. As a result, normalization information is reflected on the judgment and a desired data sequence is judged by Viterbi-decoding any one of a plurality of data sequences with simple processing without useless processing.

Description

technical field [0001] The present invention relates to a decoding device, a communication device and a decoding method, in which a data sequence is judged by simultaneously receiving a plurality of data sequences and performing Viterbi decoding on them. More particularly, the present invention is suitable for use in combination with a Viterbi decoder and a data decision unit, wherein, for example, the data decision unit can be applied to an HS-SCCH (shared control channel for HS-DSCH) Channel receiving system, which is part of the W-CDMA (Wideband Code Division Multiple Access) system. Background technique [0002] In a decoding device, a plurality of data sequences are received simultaneously, any one of which is encoded by a data sequence from the plurality of data sequences and assigned to each predetermined communication device, and in the decoding device Viterbi decoding is then performed on any one of the plurality of data sequences to determine an expected data sequ...

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Problems solved by technology

[0015] However, in the above first judgment process, even if it is clearly determined that the likelihood of a certain data sequence is low in data sequence decoding, the data sequence must be decoded for comparison, thereby inevitably increase the useless processing

[0016] Similarly, in order to compare the likelihood, a large amount of data to be processed is added in the above second decision process, and the process will become very complicated

[0017] Furthermore, in the cited patent reference 1, the decoder allows the chain-back memory to hold those determined bits from previous processing cycles as a buffer, so that a full chain-back does not always have to be performed (chain-back) operation, but cannot stop the decoding process itself

In this way, as mentioned above, there will also be useless processing here.

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