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A peripheral interface circuit for an i/o node of a computer system

A computer system and peripheral interface technology, applied in the field of peripheral transaction processing, can solve problems such as data packet bus structure stalls

Inactive Publication Date: 2005-07-13
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Deadlocks can cause further stalls on the packet bus structure

Method used

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  • A peripheral interface circuit for an i/o node of a computer system
  • A peripheral interface circuit for an i/o node of a computer system
  • A peripheral interface circuit for an i/o node of a computer system

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Embodiment Construction

[0026] While the invention is susceptible to various modifications and alternative forms, certain specific embodiments of the invention have been set forth by way of illustration and described in detail herein. However, it should be understood that these illustrations and detailed descriptions are not intended to limit the invention to the specific form disclosed, on the contrary, the invention will cover the spirit and scope of the invention defined by the appended claims. All modifications, equivalents and alternatives.

[0027] Referring now to FIG. 1, a block diagram of one specific embodiment of a computer system is shown. The computer system includes processors 10A-10D, with an associated packet bus 15 connecting each processor. Each portion of the associated packet bus 15 may form a point-to-point link between the processors 10A-10D and each other. Although four processors are shown using point-to-point links, note that other numbers of processors may be used, as well...

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Abstract

The invention discloses a peripheral interface circuit for an I / O node of a computer system. The peripheral interface circuit of the I / O node of the computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a plurality of first buffers, each buffer corresponding to a respective one of the plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a plurality of second buffers, wherein each buffer corresponds to a respective one of the plurality of virtual channels. The bus interface circuit may be configured to convert selected packet commands stored in the first buffer circuit into commands suitable for transmission on the peripheral bus.

Description

technical field [0001] The present invention relates to computer system input / output, particularly peripheral transaction processing within an input / output node. Background technique [0002] In a typical computer system, one or more processors communicate with various input / output (I / O) devices via one or more buses. These I / O devices can be connected to these processors through I / O bridges, which manage the transfer of information between the peripheral bus connected to these I / O devices and the shared bus connected to these processors . In addition, I / O bridges can manage the transfer of information between system memory and these I / O devices or between system memory and these processors. [0003] Unfortunately, many bus systems have several disadvantages. For example, connecting multiple devices to a bus can cause the device drive signals on the bus to exhibit large capacitance values. In addition, multiple connection points on the shared bus create signal reflection...

Claims

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Application Information

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IPC IPC(8): G06F13/36G06F13/12G06F13/362
CPCG06F13/128
Inventor T·阿斯卡尔L·D·休伊特E·G·钱伯斯
Owner GLOBALFOUNDRIES INC