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Accelerating decoder

A decoder, decoded technology, applied in other decoding technologies, error correction/detection by combining multiple code structures, digital transmission systems, etc.

Inactive Publication Date: 2011-03-09
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with conventional accelerated decoders, the error distribution pattern contained in the output decoded data is not as bursty or random as desired

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0061] figure 1 is a block diagram of the accelerated decoder according to the first embodiment of the present invention, wherein ya, yb, and yc represent the received signals affected by noise and attenuation due to passing through the communication path of the coded data xa, xb, and xc output by the transmitting end. The coded data xa is the information data u itself, the coded data xb is the data obtained by convolutionally coding the information data u, and the coded data xc is the data obtained by interleaving the information data u and then convolutionally coding the interleaved result.

[0062] Received data memory 51 stores all received signals ya, yb, yc in units of accelerated code units, and readout unit 52 reads received data ya, yb, yc from the memory at an appropriate moment and inputs the data into First and second primary decoders (DEC1, DEC2) 53,54. The first and second primary decoders 53, 54 perform the decoding process according to the well-known MAP (Max...

no. 2 example

[0076] image 3 An embodiment of an accelerated decoder is shown, where a single primary decoder is employed.

[0077] Here a primary decoder 21 is implemented in a time-sharing manner: (1) by figure 1 The first primary decoder 53 uses the received signal Ya, yb and decodes the second half of the result to perform the decoding process (the first half of the decoding process), and (2) by figure 1 The second primary decoder 54 performs a decoding process using the received signal yc and the result of decoding the first half (second half of the decoding process). In other words, the timing of the decoding operation is divided into a first timing at which the first (first half) decoding process is performed and a second timing at which the second (second half) decoding process is performed, the first half of the decoding process at the first timing is executed, and the second half of the decoding process is executed at the second timing.

[0078] At the first timing moment wh...

no. 3 example

[0084] In prior art, such as Figure 18 As shown in (b), the error is dispersed among multiple information blocks, and the error rate on a per-block basis increases, and if the retransmission control is performed in units of information blocks, the number of retransmissions will increase . Therefore, in the case of retransmission, it is more advantageous to concentrate errors than to disperse them. With convolutional coding, the error distribution pattern in the decoding result of the primary decoder is bursty in nature. Utilizing this property makes it possible to directly output the decoding result without interleaving or deinterleaving.

[0085] Figure 4 The block diagram of shows the third embodiment of the present invention, in which the error generation pattern contained in the decoding result (decoded data) appears to be bursty.

[0086] The interleaver 30 interleaves the received signal ya and inputs the result to the first primary decoder 31 . The first primary ...

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Abstract

The errors in the result of checking accelerated decode is made at the same time of repeating converse decode. If no error is checked, then the result of decode is outputted. The decode process doesn't go on even though the decode operation is in repeat. Further more when the decoding where is preset decoding time is made, the error numbers checked in the result of decode is monitored. If the checked error numbers is less than a presetting value, then the decode operation is repeated. The one of first and second decoding results outputted by first and second decoders composing the accelerating decoder are selected as proper result that is outputted.

Description

[0001] The present invention is a divisional application of the No. 99816223.X patent application whose filing date is March 1, 1999 and whose invention name is "accelerated decoder". technical field [0002] The present invention relates to a turbo decoder, and more particularly, to a turbo decoder that decodes a received signal using the results obtained by decoding it, and then uses the successively obtained decoding results to set Repeat the decoding a certain number of times, and output the decoded data. Background technique [0003] Error correcting codes are used in various systems to correct errors contained in received or reconstructed information so that the original information can be correctly decoded. For example, error correcting codes are applied to those cases where data is to be transmitted without error when performing mobile communication, FAX (facsimile) or other data communication, and where data is to be reconstructed without error from a mass storag...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/45H03M13/29H04L1/00
Inventor 矢野哲也大渕一央川端和生
Owner FUJITSU LTD
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